tangxifan 61163de580 [Testbench] Correct path to post-pnR netlists and prepare for sign-off on FPGA with reset		2020-12-02 12:00:28 -07:00
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postpnr/verilog_testbench	[Testbench] Correct path to post-pnR netlists and prepare for sign-off on FPGA with reset	2020-12-02 12:00:28 -07:00
prepnr/verilog_testbench	[Testbench] Add configuration chain test benches for pre- and post- pnr simulation	2020-11-18 15:58:00 -07:00