SOFA/SynRepoConfig/sync_files_qlsofa_hd.csv

248 B

1SrcLoc, DestLoc
2FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/,OpenFPGA_task
3FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
4FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top*.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v