mirror of https://github.com/lnis-uofu/SOFA.git
39 lines
1.0 KiB
Verilog
39 lines
1.0 KiB
Verilog
`timescale 1ns / 10ps
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module FFEDataMemoryMux (
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input Select,
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input [9:0] ReadAddressIn0,
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input [9:0] ReadAddressIn1,
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output[9:0] ReadAddressOut,
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input [9:0] WriteAddressIn0,
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input [9:0] WriteAddressIn1,
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output[9:0] WriteAddressOut,
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input [35:0] DataToMemoryIn0,
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input [35:0] DataToMemoryIn1,
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output[35:0] DataToMemoryOut,
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input [35:0] DataFromMemoryIn0,
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input [35:0] DataFromMemoryIn1,
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output[35:0] DataFromMemoryOut,
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input ReadEnable0,
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input ReadEnable1,
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output ReadEnable,
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input WriteEnable0,
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input WriteEnable1,
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output WriteEnable
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);
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assign ReadAddressOut = (Select) ? ReadAddressIn1 : ReadAddressIn0;
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assign WriteAddressOut = (Select) ? WriteAddressIn1 : WriteAddressIn0;
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assign DataToMemoryOut = (Select) ? DataToMemoryIn1 : DataToMemoryIn0;
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assign DataFromMemoryOut = (Select) ? DataFromMemoryIn1 : DataFromMemoryIn0;
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assign ReadEnable = (Select) ? ReadEnable1 : ReadEnable0;
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assign WriteEnable = (Select) ? WriteEnable1 : WriteEnable0;
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endmodule
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