mirror of https://github.com/lnis-uofu/SOFA.git
96 lines
3.7 KiB
Verilog
96 lines
3.7 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// Discrete Cosine Transform Synthesis Test ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// Synthesis results: ////
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//// ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: dct_syn.v,v 1.3 2002-10-31 12:50:03 rherveille Exp $
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//
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// $Date: 2002-10-31 12:50:03 $
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// $Revision: 1.3 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/10/23 09:06:59 rherveille
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// Improved many files.
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// Fixed some bugs in Run-Length-Encoder.
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// Removed dependency on ud_cnt and ro_cnt.
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// Started (Motion)JPEG hardware encoder project.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module dct_syn(clk, ena, rst, dstrb, din, dout, den);
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input clk;
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input ena;
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input rst;
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input dstrb;
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input [7:0] din;
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output [11:0] dout;
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output den;
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//
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// DCT unit
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//
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// As little as 11bits coefficients can be used while
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// all errors remain in the decimal bit range (dout[0])
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// total errors = 5(14bit resolution)
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// = 12(13bit resolution)
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// = 26(12bit resolution)
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// = 54(11bit resolution)
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fdct #(13) dut (
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.clk(clk),
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.ena(1'b1),
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.rst(rst),
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.dstrb(dstrb),
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.din(din),
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.dout(dout),
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.douten(den)
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);
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endmodule
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