mirror of https://github.com/lnis-uofu/SOFA.git
30 lines
422 B
Verilog
30 lines
422 B
Verilog
/////////////////////////////////////////
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// Functionality: 2-input AND with clocked
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// and combinational outputs
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// Author: Xifan Tang
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////////////////////////////////////////
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`timescale 1ns / 1ps
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module and2_latch(
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a,
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b,
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clk,
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c,
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d);
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input wire clk;
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input wire a;
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input wire b;
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output wire c;
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output reg d;
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assign c = a & b;
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always @(posedge clk) begin
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d <= c;
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end
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endmodule
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