mirror of https://github.com/lnis-uofu/SOFA.git
57 lines
2.4 KiB
Verilog
57 lines
2.4 KiB
Verilog
`timescale 1ns/1ps
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//-----------------------------------------------------
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// Function : An embedded I/O with
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// - An I/O isolation signal to set
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// the I/O in input mode. This is to avoid
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// any unexpected output signals to damage
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// circuits outside the FPGA due to configurable
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// memories are not properly initialized
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// This feature may not be needed if the configurable
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// memory cell has a built-in set/reset functionality
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// - Internal protection circuitry to ensure
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// clean signals at all the SOC I/O ports
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// This is to avoid
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// - output any random signal
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// when the I/O is in input mode, also avoid
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// - driven by any random signal
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// when the I/O is output mode
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//
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// Note: This cell is built with Standard Cells from HD library
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// It is already technology mapped and can be directly used
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// for physical design
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//-----------------------------------------------------
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module EMBEDDED_IO_HD (
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input SOC_IN, // Input to drive the inpad signal
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output SOC_OUT, // Output the outpad signal
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output SOC_DIR, // Output the directionality
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output FPGA_IN, // Input data to FPGA
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input FPGA_OUT, // Output data from FPGA
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input FPGA_DIR, // direction control
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input IO_ISOL_N // Isolation enable signal
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);
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wire SOC_DIR_N;
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// Use drive-strength 4 for a high fan-out from SoC components
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sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE (.B_N(IO_ISOL_N),
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.A(FPGA_DIR),
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.X(SOC_DIR)
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);
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// Use drive-strength 4 for a high fan-out from global routing architecture
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sky130_fd_sc_hd__inv_1 INV_SOC_DIR (.A(SOC_DIR), .Y(SOC_DIR_N));
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sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE (.TE_B(SOC_DIR_N),
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.A(SOC_IN),
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.Z(FPGA_IN)
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);
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// Use drive-strength 4 for a potential high fan-out from SoC components
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sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE (.TE_B(SOC_DIR),
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.A(FPGA_OUT),
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.Z(SOC_OUT)
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);
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endmodule
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