mirror of https://github.com/lnis-uofu/SOFA.git
162 lines
8.3 KiB
Python
162 lines
8.3 KiB
Python
#####################################################################
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# Python script generate Verilog codes for the Caravel wrapper
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# which interface the FPGA fabric and other SoC components
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# This script will
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# - generate the Verilog codes to connect FPGA inputs to Wishbone and Logic analyzer
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# - generate the Verilog codes to connect FPGA outputs to Wishbone and Logic analyzer
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#####################################################################
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import os
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from os.path import dirname, abspath, isfile
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import shutil
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import re
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import argparse
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import logging
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import json
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#####################################################################
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# Initialize logger
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#####################################################################
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logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.DEBUG)
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#####################################################################
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# Parse the options
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# - OpenFPGA root path is a manadatory option
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#####################################################################
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parser = argparse.ArgumentParser(
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description='Generator for technology-mapped wrapper')
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parser.add_argument('--template_netlist', default='caravel_fpga_wrapper_hd_template.v',
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help='Specify template verilog netlist')
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parser.add_argument('--pin_assignment_file', required=True,
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help='Specify the json file constaining pin assignment information')
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parser.add_argument('--output_verilog', default='caravel_fpga_wrapper_hd.v',
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help='Specify output verilog file path')
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args = parser.parse_args()
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#####################################################################
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# Check options:
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# - Input json file must be valid
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# Otherwise, error out
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#####################################################################
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if not isfile(args.pin_assignment_file):
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logging.error("Invalid pin assignment file: " + args.pin_assignment_file + "\nFile does not exist!\n")
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exit(1)
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#####################################################################
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# Parse the json file
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#####################################################################
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json_file = open(args.pin_assignment_file, "r")
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pin_data = json.load(json_file)
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#####################################################################
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# A function to parse pin range from json data
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# JSON pin range format is LSB:MSB
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# Return pin range format is [LSB, MSB] as a list
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#####################################################################
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def parse_json_pin_range(json_range) :
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pin_range = json_range.split(':')
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assert(2 == len(pin_range))
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return pin_range
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#####################################################################
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# Generate wrapper lines
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#####################################################################
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netlist_lines = []
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# Walk through the array containing the pin information
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for pin_info in pin_data['pins']:
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# Deposit a tab to respect the HDL coding indent
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curr_line = " "
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# TODO: Check codes that ensure the pin index should match
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#
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# Branch on the types of connnections:
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# - FPGA I/O to Caravel GPIO
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if (("io" == pin_info['fpga_pin_type']) and ("gpio" == pin_info['caravel_pin_type'][0])):
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# Should have only 1 port in caravel
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assert(1 == len(pin_info['caravel_pin_type']))
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# Get pin range
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fpga_io_pin_range = parse_json_pin_range(pin_info['fpga_pin_index'])
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# Connect all the input, output and direction port
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# FPGA input <- Caravel input
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# FPGA output -> Caravel output
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# FPGA direction -> Caravel direction
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curr_line += "assign " + pin_data['fpga_gpio_input_name']
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netlist_lines.append(curr_line + "\n")
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if ((ipin < num_wishbone_pins) and (ipin < num_logic_analyzer_pins)):
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# If this is an input pin of wishbone interface, whose postfix is '_i', we use MUX
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# otherwise, this is an output pin, we just wire the input to logic analyzer
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if ((wishbone_pins[ipin].endswith("_i")) or (re.search(r'_i\[\d+\]$', wishbone_pins[ipin], re.M | re.I))):
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##############################################################
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# SOC INPUT will be directly driven by either
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# - the Wishbone input
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# or
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# - the logic analyzer input
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# through a multiplexer controlled by the signal 'wb_la_switch
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curr_line = " " + "sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_" + str(135 - ipin) + "_MUX (.S(wb_la_switch), .A1(" + str(
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wishbone_pins[ipin]) + "), .A0(" + str(logic_analyzer_pins[ipin][0]) + "), .X(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[" + str(135 - ipin) + "]));"
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netlist_lines.append(curr_line + "\n")
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##############################################################
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# SOC OUTPUT will drive an output of logic analyzer
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# since this I/O is going to interface a Wishbone input only
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curr_line = " " + "assign " + \
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str(logic_analyzer_pins[ipin][1]) + \
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" = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[" + str(135 - ipin) + "];"
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netlist_lines.append(curr_line + "\n")
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elif ((wishbone_pins[ipin].endswith("_o")) or (re.search(r'_o\[\d+\]$', wishbone_pins[ipin], re.M | re.I))):
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##############################################################
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# SOC INPUT will be directly driven by logic analyzer
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# since this I/O is going to interface a Wishbone output only
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curr_line = " " + "assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[" + str(
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135 - ipin) + "] = " + str(logic_analyzer_pins[ipin][0]) + ";"
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netlist_lines.append(curr_line + "\n")
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##############################################################
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# SOC OUTPUT will drive the Wishbone output through a tri-state buffer
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# As the buffer is enabled by logic '0', we use the inverted 'wb_la_switch'
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curr_line = " " + "sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_" + str(135 - ipin) + "_DEMUX_WB (" + \
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".TE_B(wb_la_switch_b), " + \
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".A(" + "gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[" + str(135 - ipin) + "]), " + \
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".Z(" + str(wishbone_pins[ipin]) + ")" + \
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");"
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netlist_lines.append(curr_line + "\n")
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##############################################################
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# SOC OUTPUT will also drive the Logic Analyzer output through a tri-state buffer
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# As the buffer is enabled by logic '0', we use the 'wb_la_switch'
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curr_line = " " + "sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_" + str(135 - ipin) + "_DEMUX_LA (" + \
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".TE_B(wb_la_switch), " + \
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".A(" + "gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[" + str(135 - ipin) + "]), " + \
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".Z(" + str(logic_analyzer_pins[ipin][1]) + ")" + \
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");"
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netlist_lines.append(curr_line + "\n")
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elif ((ipin >= num_wishbone_pins) and (ipin < num_logic_analyzer_pins)):
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##############################################################
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# SOC INPUT will be directly driven by logic analyzer
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# since this I/O is going to interface logic analyzer input only
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curr_line = " " + "assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[" + str(
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135 - ipin) + "] = " + str(logic_analyzer_pins[ipin][0]) + ";"
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netlist_lines.append(curr_line + "\n")
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##############################################################
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# SOC OUTPUT will directly drive logic analyzer
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# since this I/O is going to interface logic analyzer output only
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curr_line = " " + "assign " + \
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str(logic_analyzer_pins[ipin][1]) + \
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" = gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[" + str(135 - ipin) + "];"
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netlist_lines.append(curr_line + "\n")
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if isfile(args.output_verilog):
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os.remove(args.output_verilog)
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with open(args.template_netlist, "r") as wp:
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template_netlist = wp.readlines()
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for line_num, eachline in enumerate(template_netlist):
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if "Autogenerate code start" in eachline:
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logging.info(f"Inserting on line {line_num}")
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template_netlist[line_num+1:line_num+1] = netlist_lines
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logging.info("Outputting HDL codes to " +
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str(args.output_verilog) + " ...")
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vlog_file = open(args.output_verilog, "w")
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vlog_file.write("".join(template_netlist))
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vlog_file.close()
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break
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