mirror of https://github.com/lnis-uofu/SOFA.git
97 lines
4.2 KiB
Python
97 lines
4.2 KiB
Python
#####################################################################
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# Python script to convert pre-PnR Verilog testbench
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# to post-PnR Verilog testbench
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# This script will
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# - Add ports required by post-PnR Verilog module
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# - Scan-chain head and tail ports
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# - Add signal stimuli for the scan-chain head and tails
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# - Rename fpga_top to fpga_core when instanciate Design Under Test (DUT)
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#####################################################################
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import os
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from os.path import dirname, abspath, isfile
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import shutil
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import re
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import argparse
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import logging
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#####################################################################
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# Initialize logger
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#####################################################################
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logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.DEBUG)
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#####################################################################
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# Parse the options
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#####################################################################
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parser = argparse.ArgumentParser(description='Converter for post-PnR Verilog testbench')
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parser.add_argument('--pre_pnr_testbench', required=True,
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help='Specify the file path for the pre-PnR Verilog testbench as input')
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parser.add_argument('--post_pnr_testbench', required=True,
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help='Specify the file path for the post-PnR Verilog testbench to be outputted')
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args = parser.parse_args()
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#####################################################################
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# Check options:
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# - Input file must be valid
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# Otherwise, error out
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# - Remove any output file if already exist
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# TODO: give a warning when remove files
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#####################################################################
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if not isfile(args.pre_pnr_testbench):
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logging.error("Invalid pre-PnR testbench: " + args.pre_pnr_testbench + "\nFile does not exist!\n")
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exit(1)
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if isfile(args.post_pnr_testbench):
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logging.warn("Remove existing post-PnR testbench: " + args.post_pnr_testbench + "!\n")
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os.remove(args.post_pnr_testbench)
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#####################################################################
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# Open the post-pnr Verilog testbench and start modification
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#####################################################################
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logging.info("Converting pre-PnR testbench:"+ args.pre_pnr_testbench)
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logging.info(" To post-PnR testbench:"+ args.post_pnr_testbench)
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# Create output file handler
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tb_file = open(args.post_pnr_testbench, "w")
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# Read line by line from pre-PnR testbench
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with open(args.pre_pnr_testbench, "r") as wp:
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template_netlist = wp.readlines()
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for line_num, curr_line in enumerate(template_netlist):
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# If the current line satisfy the following conditions
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# It should be modified and outputted to post-PnR Verilog testbenches
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# Other lines can be directly copied to post-PnR Verilog testbenches
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line2output = curr_line \
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# Condition A:
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# Add post_pnr to top-level module name
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if (curr_line.startswith("module")):
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line2output = re.sub("autocheck_top_tb;$", "post_pnr_autocheck_top_tb;", curr_line)
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# Add sc_head and sc_tail wire definition after ccff tail definition
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# Condition B:
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# Add sc_head and sc_tail wire definition after ccff tail definition
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if (curr_line == "wire [0:0] ccff_tail;\n"):
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line2output = line2output \
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+ "// ---- Scan-chain head ----\n" \
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+ "wire [0:0] sc_head;\n" \
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+ "// ---- Scan-chain tail ----\n" \
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+ "wire [0:0] sc_tail;\n"
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# Condition C:
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# Assign an initial value to sc_head after other ports
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elif (curr_line == "\tassign IO_ISOL_N[0] = 1'b1;\n"):
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line2output = line2output \
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+ "\tassign sc_head[0] = 1'b0;\n"
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# Condition D:
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# Replace fpga_top with fpga_core in DUT instanciation
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elif (curr_line == "\tfpga_top FPGA_DUT (\n"):
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line2output = "\tfpga_core FPGA_DUT (\n"
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# Condition E:
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# Add sc_head and sc_tail to the port mapping of FPGA core instance
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elif (curr_line == "\t\t.ccff_tail(ccff_tail[0]));\n"):
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line2output = "\t\t.ccff_tail(ccff_tail[0]),\n" \
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+ "\t\t.sc_head(sc_head[0]),\n" \
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+ "\t\t.sc_tail(sc_tail[0])\n" \
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+ "\t\t);\n"
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tb_file.write(line2output)
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tb_file.close()
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logging.info("Done")
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