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SOFA/FPGA1212_FC_HD_SKY_PNR
History
Ganesh Gore 82767cd1b2 Updated 12x12 design skipped module GDSs 2020-11-10 15:37:00 -07:00
..
FPGA1212_FC_HD_SKY_Verilog Updated 12x12 design skipped module GDSs 2020-11-10 15:37:00 -07:00
FPGA1212_FC_HD_SKY_task Updated 12x12 design skipped module GDSs 2020-11-10 15:37:00 -07:00
fpga_core Updated 12x12 design skipped module GDSs 2020-11-10 15:37:00 -07:00
modules Added 12x12 FPGA design with SKY130_SC_HD cells 2020-10-28 12:41:37 -06:00
README.md Added 12x12 FPGA design with SKY130_SC_HD cells 2020-10-28 12:41:37 -06:00

README.md

FPGA1212_FC_HD_SKY_PNR

12x12 FPGA designed using hierarchical flow and SKY130_FD_SC_HD.

Directory Structure

  • FPGA1212_HIER_SKY_task :- OpenFPGA task directory and all related files
  • FPGA1212_HIER_SKY_Verilog :- Verilog-netlist used for this design
  • modules :- Final files of each module (lef,def,spef,v,gds)
  • fpga_core :- Final files of fpga_core (eFPGA design)
  • fpga_top :- Reserved for design with GPIOs or caravel

Checks

  • .tech file DRC - Clean
  • Timing SignOff - Clean

Pending

  • DRC SignOff
  • LVS SignOff
  • PostPnR function simulation