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SOFA/SCRIPT/openfpga_simulation_setting
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tangxifan b966829566 [Script] Force a fixed number of clock cycles in simulation to avoid false-positive 2020-12-02 17:50:23 -07:00
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efpga_12x12_sim_openfpga.xml [Script] Force a fixed number of clock cycles in simulation to avoid false-positive 2020-12-02 17:50:23 -07:00