tangxifan 39b2b99ac2 [Doc] Update I/O switch by considering clock switches		2020-11-18 19:47:24 -07:00
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clb_arch.png	[Doc] Add detailed architecture schematic	2020-11-17 11:44:57 -07:00
embedded_io_schematic.png	[Doc] Update I/O circuitry details	2020-11-17 19:31:04 -07:00
fabric_scan_chain.png	[Doc] Add detailed architecture schematic	2020-11-17 11:44:57 -07:00
fle_arch.png	[Doc] Add missing figures	2020-11-12 22:05:44 -07:00
fpga_arch.png	[Doc] Add detailed architecture schematic	2020-11-17 11:44:57 -07:00
fpga_io_map_logic_analyzer_mode.png	[Doc] Update I/O arrangement to avoid congestion in backend	2020-11-18 19:11:35 -07:00
fpga_io_map_wishbone_mode.png	[Doc] Update I/O arrangement to avoid congestion in backend	2020-11-18 19:11:35 -07:00
fpga_io_switch.png	[Doc] Update I/O switch by considering clock switches	2020-11-18 19:47:24 -07:00