mirror of https://github.com/lnis-uofu/SOFA.git
60 lines
2.8 KiB
Bash
60 lines
2.8 KiB
Bash
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# = = = = = = = = = = = = = = Variables Sections = = = = = = = = = = = = = = =
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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source ../../openfpga-physical/conf_template.sh
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export_ PROJ_NAME = FPGA88_SOFA_A # Project Name
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export_ FPGA_SIZE_X = 8 # Grid X Size
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export_ FPGA_SIZE_Y = 8 # Grid Y Size
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export_ LAYOUT = "FPGA88"
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export_ DESIGN_STYLE = hier
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export_ TECHNOLOGY = "skywater"
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export_ TASK_DIR_NAME = "${PROJ_NAME}_task"
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export_ VERILOG_PROJ_DIR = "${RELEASE_DIRECTORY}/${PROJ_NAME}_verilog"
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export_ GENERATE_FABRIC_KEY = "../CommonFiles/render_sofa_a_fabric_key.py"
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export_ NETLIST_SYNTH_SCRIPT = "../CommonFiles/sofa_netlist_synth_script.sh"
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export_ RESTRUCT_NETLIST = "../CommonFiles/restructure_fabric_sofa_a.py"
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export_ CUSTOM_MODULES_LIST = "./${TASK_DIR_NAME}/CustomModules/custom_module.txt"
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export_ GLOBAL_FT_SCRIPT = "../CommonFiles/generate_global_signals_connectivity.py"
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export_ CLOCK_FT_SCRIPT = "../CommonFiles/generate_clock_connectivity.py"
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# Complete Chip (fpga_top) or eFPGA (fpga_core)
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export_ DESIGN_NAME = fpga_core
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# Pin Information Source Automatic or Sheet
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export_ PIN_MAP = Automatic
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export_ PIN_MAP_CSV_SPREADSHEET_LINK = "" # Required only if PIN_MAP==Sheet
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# Core Dimension, requires if DESIGN_NAME=fpga_core
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# if DESIGN_NAME=fpga_top its Optional if defined it overrides the
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# Calculated DIE_DIMENSION
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export_ DIE_DIMENSION = 3200
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Derived Or Fixed Variables
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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export_ OPENFPGA_ENGINE_PATH = ${OPENFPGA_PATH}
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export_ TASK_DIR_NAME = ${PROJ_NAME}_task
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export_ VERILOG_PROJ_DIR = ${PROJ_NAME}_verilog
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export_ SPY_HACK_FILE = ${TASK_DIR_NAME}/spy_hack.txt
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export_ POST_OPENFPGA_SCRIPT = ./PostOpenFPGAScript.sh
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export_ POST_GENERATION_SCRIPT = ./generate_scandef_and_case_analysis.sh
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export_ TAPEOUT_DIRECTORY = /research/ece/lnis/USERS/DARPA_ERI/Tapeout/SOFA
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export_ TAPEOUT_SCRIPT =
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export_ RENDER_FABRIC_SCRIPT = "../CommonFiles/render_sofa_a.py"
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# PNR RELATED FLOW
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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export_ INIT_DESIGN_INPUT="ASCII"
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Extra variables availble during flow (suuffix FLOWVAR_)
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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export_ FLOWVAR_STANDARD_CELLS="sc_hd"
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