Ganesh Gore ec9a02f9e0 Added 12x12 FPGA design with SKY130_SC_HD cells		2020-10-28 12:41:37 -06:00
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cbx_1__0__icv_in_design.nominal_25.spef	Added 12x12 FPGA design with SKY130_SC_HD cells	2020-10-28 12:41:37 -06:00
cbx_1__1__icv_in_design.nominal_25.spef	Added 12x12 FPGA design with SKY130_SC_HD cells	2020-10-28 12:41:37 -06:00
cbx_1__2__icv_in_design.nominal_25.spef	Added 12x12 FPGA design with SKY130_SC_HD cells	2020-10-28 12:41:37 -06:00
cby_0__1__icv_in_design.nominal_25.spef	Added 12x12 FPGA design with SKY130_SC_HD cells	2020-10-28 12:41:37 -06:00
cby_1__1__icv_in_design.nominal_25.spef	Added 12x12 FPGA design with SKY130_SC_HD cells	2020-10-28 12:41:37 -06:00
sb_0__0__icv_in_design.nominal_25.spef	Added 12x12 FPGA design with SKY130_SC_HD cells	2020-10-28 12:41:37 -06:00
sb_0__1__icv_in_design.nominal_25.spef	Added 12x12 FPGA design with SKY130_SC_HD cells	2020-10-28 12:41:37 -06:00
sb_0__2__icv_in_design.nominal_25.spef	Added 12x12 FPGA design with SKY130_SC_HD cells	2020-10-28 12:41:37 -06:00
sb_1__0__icv_in_design.nominal_25.spef	Added 12x12 FPGA design with SKY130_SC_HD cells	2020-10-28 12:41:37 -06:00
sb_1__1__icv_in_design.nominal_25.spef	Added 12x12 FPGA design with SKY130_SC_HD cells	2020-10-28 12:41:37 -06:00
sb_1__2__icv_in_design.nominal_25.spef	Added 12x12 FPGA design with SKY130_SC_HD cells	2020-10-28 12:41:37 -06:00
sb_2__0__icv_in_design.nominal_25.spef	Added 12x12 FPGA design with SKY130_SC_HD cells	2020-10-28 12:41:37 -06:00
sb_2__1__icv_in_design.nominal_25.spef	Added 12x12 FPGA design with SKY130_SC_HD cells	2020-10-28 12:41:37 -06:00
sb_2__2__icv_in_design.nominal_25.spef	Added 12x12 FPGA design with SKY130_SC_HD cells	2020-10-28 12:41:37 -06:00