mirror of https://github.com/lnis-uofu/SOFA.git
22 lines
488 B
Verilog
22 lines
488 B
Verilog
//
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// Copyright (c) 2020 QuickLogic Corporation. All Rights Reserved.
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//
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// Description :
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// Example of asimple 16 bit up counter in Verilog HDL
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//
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// Version 1.0 : Initial Creation
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//
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module top (clk, reset, enable, count);
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input clk, reset, enable;
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output [15:0] count;
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reg [15:0] count;
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always @ (posedge clk)
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if (reset == 1'b1) begin
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count <= 0;
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end else if ( enable == 1'b1) begin
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count <= count + 1;
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end
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endmodule
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