mirror of https://github.com/lnis-uofu/SOFA.git
252 lines
6.6 KiB
Verilog
252 lines
6.6 KiB
Verilog
`timescale 1 ns / 1 ps
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`define POWER_UP_TIME_PERIOD 200
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`define SOC_RESET_TIME_PERIOD 2000
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`define SOC_SETUP_TIME_PERIOD 200*2001
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`define SOC_CLOCK_PERIOD 12.5
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`define FPGA_PROG_CLOCK_PERIOD 12.5
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`define FPGA_CLOCK_PERIOD 12.5
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module ccff_test_post_pnr_caravel_autocheck_top_tb;
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reg clock;
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reg RSTB;
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reg power1, power2;
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reg power3, power4;
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wire gpio;
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wire [37:0] mprj_io;
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// ----- Local wires for control ports of FPGA fabric -----
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wire [0:0] pReset;
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reg [0:0] prog_clock_reg;
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wire [0:0] prog_clk;
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wire [0:0] prog_clock;
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wire [0:0] Test_en;
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wire [0:0] Reset;
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reg [0:0] op_clock_reg;
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wire [0:0] op_clk;
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wire [0:0] op_clock;
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reg [0:0] prog_reset;
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reg [0:0] greset;
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// ---- Configuration-chain head -----
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reg [0:0] ccff_head;
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// ---- Configuration-chain tail -----
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wire [0:0] ccff_tail;
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// ---- Scan-chain head -----
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wire [0:0] sc_head;
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// ---- Scan-chain tail -----
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wire [0:0] sc_tail;
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wire [0:0] IO_ISOL_N;
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// ----- Counters for error checking -----
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integer num_prog_cycles = 0;
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integer num_errors = 0;
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integer num_checked_points = 0;
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// Indicate when SoC setup phase should be finished
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reg soc_setup_done = 0;
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// Indicate when configuration should be finished
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reg config_done = 0;
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initial
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begin
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config_done = 1'b0;
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soc_setup_done = 1'b0;
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end
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// ----- Begin raw programming clock signal generation -----
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initial
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begin
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prog_clock_reg[0] = 1'b0;
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end
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always
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begin
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#(`FPGA_PROG_CLOCK_PERIOD) prog_clock_reg[0] = ~prog_clock_reg[0];
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end
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// ----- End raw programming clock signal generation -----
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// ----- Begin raw operating clock signal generation -----
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initial
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begin
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op_clock_reg[0] = 1'b0;
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end
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// ----- End raw operating clock signal generation -----
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// ----- Actual operating clock is triggered only when config_done is enabled -----
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assign prog_clock[0] = prog_clock_reg[0] & (~prog_reset[0]);
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assign op_clock[0] = op_clock_reg[0];
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// ----- Begin programming reset signal generation -----
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initial
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begin
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prog_reset[0] = 1'b1;
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#(`SOC_SETUP_TIME_PERIOD + 2 * `FPGA_PROG_CLOCK_PERIOD) prog_reset[0] = 1'b0;
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end
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// ----- End programming reset signal generation -----
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// ----- Begin operating reset signal generation -----
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// ----- Reset signal is disabled always -----
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initial
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begin
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greset[0] = 1'b1;
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end
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// ----- End operating reset signal generation -----
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// ----- Begin connecting global ports of FPGA fabric to stimuli -----
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assign op_clk[0] = op_clock[0];
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assign prog_clk[0] = prog_clock[0];
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assign pReset[0] = ~prog_reset[0];
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assign Reset[0] = ~greset[0];
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assign Test_en[0] = 1'b0;
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assign sc_head[0] = 1'b0;
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assign IO_ISOL_N[0] = ~greset;
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// ----- End connecting global ports of FPGA fabric to stimuli -----
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assign mprj_io[0] = Test_en;
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assign mprj_io[1] = IO_ISOL_N;
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assign mprj_io[2] = Reset;
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assign mprj_io[3] = pReset;
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assign mprj_io[12] = ccff_head;
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assign mprj_io[25] = 1'b0; // Set FPGA to interface logic analyzer by default
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assign mprj_io[26] = sc_head;
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assign mprj_io[36] = op_clk;
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assign mprj_io[37] = prog_clk;
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assign sc_tail = mprj_io[11];
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assign ccff_tail = mprj_io[35];
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assign mprj_io[10:4] = {7{1'b0}};
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assign mprj_io[24:13] = {12{1'b0}};
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assign mprj_io[34:27] = {8{1'b0}};
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// Generate a pulse after programming reset is disabled (in the 2nd clock
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// cycle). Then the head of configuration chain should be always zero
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always @(negedge prog_clock[0]) begin
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ccff_head = 1'b1;
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if (0 != num_prog_cycles) begin
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ccff_head = 1'b0;
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end
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end
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// ----- Count the number of programming cycles -------
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always @(posedge prog_clock[0]) begin
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num_prog_cycles = num_prog_cycles + 1;
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// Indicate when configuration is suppose to end
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if (`FPGA_BITSTREAM_SIZE + 1 == num_prog_cycles) begin
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config_done = 1'b1;
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end
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// Check the ccff_tail when configuration is done
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if (1'b1 == config_done) begin
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// The tail should spit a pulse after configuration is done
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// So it should be at logic '1' and then pulled down to logic '0'
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if (0 == num_checked_points) begin
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if (ccff_tail !== 1'b1) begin
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$display("Error: ccff_tail = %b", sc_tail);
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num_errors = num_errors + 1;
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end
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end
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if (1 <= num_checked_points) begin
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if (ccff_tail !== 1'b0) begin
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$display("Error: ccff_tail = %b", sc_tail);
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num_errors = num_errors + 1;
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end
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end
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num_checked_points = num_checked_points + 1;
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end
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if (2 < num_checked_points) begin
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$display("Simulation finish with %d errors", num_errors);
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// End simulation
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$finish;
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end
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end
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// External clock is used by default. Make this artificially fast for the
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// simulation. Normally this would be a slow clock and the digital PLL
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// would be the fast clock.
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always #(`SOC_CLOCK_PERIOD) clock <= (clock === 1'b0);
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initial begin
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clock = 0;
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end
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initial begin
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RSTB <= 1'b0;
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soc_setup_done <= 1'b1;
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#(`SOC_RESET_TIME_PERIOD);
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RSTB <= 1'b1; // Release reset
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soc_setup_done <= 1'b1; // We can start scff test
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end
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initial begin // Power-up sequence
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power1 <= 1'b0;
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power2 <= 1'b0;
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power3 <= 1'b0;
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power4 <= 1'b0;
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#(`POWER_UP_TIME_PERIOD);
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power1 <= 1'b1;
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#(`POWER_UP_TIME_PERIOD);
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power2 <= 1'b1;
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#(`POWER_UP_TIME_PERIOD);
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power3 <= 1'b1;
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#(`POWER_UP_TIME_PERIOD);
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power4 <= 1'b1;
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end
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wire flash_csb;
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wire flash_clk;
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wire flash_io0;
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wire flash_io1;
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wire VDD3V3 = power1;
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wire VDD1V8 = power2;
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wire USER_VDD3V3 = power3;
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wire USER_VDD1V8 = power4;
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wire VSS = 1'b0;
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caravel uut (
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.vddio (VDD3V3),
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.vssio (VSS),
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.vdda (VDD3V3),
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.vssa (VSS),
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.vccd (VDD1V8),
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.vssd (VSS),
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.vdda1 (USER_VDD3V3),
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.vdda2 (USER_VDD3V3),
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.vssa1 (VSS),
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.vssa2 (VSS),
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.vccd1 (USER_VDD1V8),
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.vccd2 (USER_VDD1V8),
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.vssd1 (VSS),
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.vssd2 (VSS),
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.clock (clock),
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.gpio (gpio),
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.mprj_io (mprj_io),
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.flash_csb(flash_csb),
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.flash_clk(flash_clk),
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.flash_io0(flash_io0),
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.flash_io1(flash_io1),
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.resetb (RSTB)
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);
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spiflash #(
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.FILENAME("/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.hex")
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) spiflash (
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.csb(flash_csb),
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.clk(flash_clk),
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.io0(flash_io0),
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.io1(flash_io1),
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.io2(), // not used
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.io3() // not used
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);
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endmodule
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