mirror of https://github.com/lnis-uofu/SOFA.git
103 lines
1.3 KiB
Verilog
103 lines
1.3 KiB
Verilog
// 5 counter with 5 clock domain
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// each counter has 130 bits
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// each counter has 21 output
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// test: placement , routing and performace for each clock domain
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module counter120bitx5(clk1,clk2,clk3,clk4,clk5,out1x,out2x,out3x,out4x,out5x,reset);
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input clk1,clk2,clk3,clk4,clk5,reset;
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output [13:0] out1x;
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output [13:0] out2x;
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output [13:0] out3x;
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output [13:0] out4x;
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output [13:0] out5x;
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reg [120:0] cnt1;
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reg [120:0] cnt2;
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reg [120:0] cnt3;
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reg [120:0] cnt4;
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reg [120:0] cnt5;
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assign out1x = {cnt1[120:115],cnt1[7:0]};
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assign out2x = {cnt2[120:115],cnt2[7:0]};
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assign out3x = {cnt3[120:115],cnt3[7:0]};
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assign out4x = {cnt4[120:115],cnt4[7:0]};
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assign out5x = {cnt5[120:115],cnt5[7:0]};
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always @(posedge clk1)
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begin
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if (reset)
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cnt1 <=1'b0;
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else
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cnt1 <= cnt1+1;
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end
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always @(posedge clk2)
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begin
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if (reset)
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cnt2 <=1'b0;
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else
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cnt2 <= cnt2 +1;
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end
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always @(posedge clk3)
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begin
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if (reset)
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cnt3 <=1'b0;
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else
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cnt3 <= cnt3 +1;
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end
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always @(posedge clk4)
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begin
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if (reset)
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cnt4 <=1'b0;
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else
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cnt4 <= cnt4 +1;
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end
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always @(posedge clk5)
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begin
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if (reset)
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cnt5 <=1'b0;
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else
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cnt5 <= cnt5 +1;
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end
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endmodule
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