tangxifan b08b77994c [HDL] Bug fix in the wrapper generator; now Wishbone clock is wired to a gpio of FPGA		2020-11-20 18:13:37 -07:00
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caravel_fpga_wrapper_hd.v	[HDL] Bug fix in the wrapper generator; now Wishbone clock is wired to a gpio of FPGA	2020-11-20 18:13:37 -07:00
caravel_fpga_wrapper_hd_template.v	[HDL] Bug fix in the wrapper generator; now Wishbone clock is wired to a gpio of FPGA	2020-11-20 18:13:37 -07:00
digital_io_hd.v	[HDL] Patch tech mapped netlists of digital I/O and remove the out-of-date behavoiral codes	2020-11-19 16:31:06 -07:00
skywater_function_verification.v	[HDL] Add preprocessing flags for running functional verification	2020-11-05 11:29:23 -07:00
wrapper_lines_generator.py	[HDL] Bug fix in the wrapper generator; now Wishbone clock is wired to a gpio of FPGA	2020-11-20 18:13:37 -07:00