mirror of https://github.com/lnis-uofu/SOFA.git
23 lines
396 B
Verilog
23 lines
396 B
Verilog
/////////////////////////////////////////
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// Functionality: 2-input AND + 2-input OR
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// This benchmark is designed to test fracturable LUTs
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// Author: Xifan Tang
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////////////////////////////////////////
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`timescale 1ns / 1ps
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module and2_or2(
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a,
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b,
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c,
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d);
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input wire a;
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input wire b;
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output wire c;
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output wire d;
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assign c = a & b;
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assign d = a | b;
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endmodule
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