Andrew Pond 0c7e74299e added Vexriscv task files		2021-04-03 11:04:14 -06:00
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k4_N8_caravel_cc_fdhd_2x2	[Script] Update openfpga task-run script to use the adhoc simulation settings tuned for Caravel SoC	2020-11-17 15:03:10 -07:00
k4_N8_caravel_cc_fdhd_12x12	[Script] Add and2_or2 benchmark to the testbench generation script for 12x12 HD FPGA	2020-11-22 13:34:53 -07:00
k4_N8_reset_softadder_caravel_cc_customhd_12x12	[Script] Add task run for custom cell FPGA architectures	2020-12-01 20:22:16 -07:00
k4_N8_reset_softadder_caravel_cc_fdhd_12x12	[Script] Increase routing chan width from 40 to 60 for version 1.2	2020-12-01 10:17:47 -07:00
k4_N8_reset_softadder_caravel_cc_fdhd_32x32	using default yosys script instead of custom script for multi_enc_decx2x4 design as custom script generated blif file is causing an assertion in openfpga. This is done temporarily to enable developers to checkin in SOFA, also requested Xifan to review this crash in openfpga.	2021-02-03 01:08:27 -08:00
vexriscv/generate_testbench/config	added Vexriscv task files	2021-04-03 11:04:14 -06:00