mirror of https://github.com/lnis-uofu/SOFA.git
109 lines
4.9 KiB
ReStructuredText
109 lines
4.9 KiB
ReStructuredText
.. _sofa_hd_timing:
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Timing Annotation
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-----------------
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.. _sofa_hd_timing_clb:
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Configurable Logic Block
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^^^^^^^^^^^^^^^^^^^^^^^^
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The path delays in :numref:`fig_sofa_hd_fle_arch_timing` are listed in :numref:`table_sofa_hd_fle_arch_timing`.
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.. _fig_sofa_hd_fle_arch_timing:
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.. figure:: ./figures/sofa_hd_fle_arch_timing.svg
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:scale: 30%
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:alt: Schematic of a logic element used in SOFA HD FPGA
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Schematic of a logic element used in SOFA HD FPGA
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.. _table_sofa_hd_fle_arch_timing:
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.. table:: Path delays of logic element in the SOFA HD FPGA
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+-------------------------+------------------------------+
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| Path / Delay | TT (unit: ns) |
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+=========================+==============================+
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| in0 -> LUT3_out[0] [1]_ | 2.31 |
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+-------------------------+------------------------------+
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| in1 -> LUT3_out[0] [1]_ | 2.31 |
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+-------------------------+------------------------------+
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| in2 -> LUT3_out[0] [1]_ | 2.31 |
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+-------------------------+------------------------------+
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| in0 -> LUT3_out[1] [1]_ | 2.31 |
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+-------------------------+------------------------------+
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| in1 -> LUT3_out[1] [1]_ | 2.31 |
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+-------------------------+------------------------------+
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| in2 -> LUT3_out[1] [1]_ | 2.31 |
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+-------------------------+------------------------------+
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| in0 -> LUT4_out [1]_ | 2.60 |
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+-------------------------+------------------------------+
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| in1 -> LUT4_out [1]_ | 2.60 |
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+-------------------------+------------------------------+
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| in2 -> LUT4_out [1]_ | 2.60 |
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+-------------------------+------------------------------+
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| in3 -> LUT4_out [1]_ | 2.60 |
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+-------------------------+------------------------------+
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| LUT3_out[0] -> A | 0.56 |
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+-------------------------+------------------------------+
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| LUT4_out[0] -> A | 0.58 |
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+-------------------------+------------------------------+
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| A -> out[0] | 0.88 |
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+-------------------------+------------------------------+
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| A -> FF[0] | 0.56 |
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+-------------------------+------------------------------+
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| FF[0] -> out[0] | 0.88 |
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+-------------------------+------------------------------+
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| LUT3_out[1] -> out[1] | 0.89 |
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+-------------------------+------------------------------+
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| LUT3_out[1] -> FF[1] | 0.56 |
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+-------------------------+------------------------------+
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| FF[1] -> out[1] | 0.89 |
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+-------------------------+------------------------------+
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| regin -> FF[0] | 0.58 |
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+-------------------------+------------------------------+
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| FF[0] -> FF[1] | 0.56 |
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+-------------------------+------------------------------+
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.. [1] The LUT input-to-output delay should be different as some inputs are close to output. However, we consider a uniform path delay considering the delay from the farest input ``in[0]`` to output. This is because VPR currently does not have LUT rebalancing techniques.
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I/O Block
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^^^^^^^^^
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The path delays in :numref:`fig_sofa_hd_embedded_io_schematic` are listed in :numref:`table_sofa_hd_io_timing`.
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.. _table_sofa_hd_io_timing:
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.. table:: Path delays of I/O circuit in the SOFA HD FPGA
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+-------------------------+------------------------------+
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| Path / Delay | TT (unit: ns) |
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+=========================+==============================+
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| SOC_IN -> FPGA_IN | 0.11 |
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+-------------------------+------------------------------+
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| FPGA_OUT -> SOC_OUT | 0.11 |
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+-------------------------+------------------------------+
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Routing Architecture
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^^^^^^^^^^^^^^^^^^^^
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The path delays in :numref:`fig_sofa_hd_routing_arch` are listed in :numref:`table_sofa_hd_routing_arch_timing`.
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.. _table_sofa_hd_routing_arch_timing:
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.. table:: Path delays of routing blocks in the SOFA HD FPGA
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+---------------------------+------------------------------+
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| Path / Delay | TT (unit: ns) |
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+===========================+==============================+
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| A -> B | 1.61 |
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+---------------------------+------------------------------+
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| A -> C | 1.61 |
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+---------------------------+------------------------------+
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| A -> D | 1.61 |
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+---------------------------+------------------------------+
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| B -> E | 1.38 |
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+---------------------------+------------------------------+
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