tangxifan a2b42c2e5f [Script] Now use variables to redirect the output directory of Verilog/SDC files		2020-10-09 16:00:41 -06:00
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skywater_generate_fabric_example_script.openfpga	[Script] Now use variables to redirect the output directory of Verilog/SDC files	2020-10-09 16:00:41 -06:00
skywater_generate_testbench_example_script.openfpga	[Flow] Add scripts to run OpenFPGA tasks	2020-10-09 14:49:54 -06:00