mirror of https://github.com/lnis-uofu/SOFA.git
112 lines
5.0 KiB
Bash
112 lines
5.0 KiB
Bash
#!/usr/bin/env bash
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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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# Design Configuration
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# ~~~~~~~~~~~~~~~~~~~~
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#
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# This file contains all the design variable use in the
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# various stages of the project
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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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# TODO unction to check if 3 arguments are passed
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export_ () { command export $1=$3; } # Export pretty printed lines
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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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# Design project variables
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# ************************
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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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export_ PROJ_NAME = "<PROJECT_NAME>" # Project Name
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export_ FPGA_SIZE_X = 0 # Grid X Size
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export_ FPGA_SIZE_Y = 0 # Grid Y Size
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export_ LAYOUT = "high_density"
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export_ TECHNOLOGY = "skywater" # Techology name label
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export_ DESIGN_NAME = "fpga_top" # Complete Chip (fpga_top) or eFPGA (fpga_core)
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export_ DIE_WIDTH = 2655.08 # Default dia width
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export_ DIE_HEIGHT = 2146.6 # Default dia height
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export_ PROJ_DIR = ${PWD} # Design roject root directory
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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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# Script configurations variable
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# ******************************
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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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export_ RENDER_FABRIC_SCRIPT = ../../openfpga-physical/render_fabric.py
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export_ GENERATE_FABRIC_KEY = ../../openfpga-physical/generate_fabric_key.py
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export_ FABRIC_KEY_PATTERN = "vertical"
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export_ GLOBAL_FT_SCRIPT = ""
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export_ CLOCK_FT_SCRIPT = ""
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export_ FLOORPLAN_SCRIPT = ""
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export_ CUSTOM_MODULES_LIST = ""
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export_ NETLIST_SYNTH_SCRIPT = ""
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export_ RESTRUCT_NETLIST = ""
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export_ PT_PRE_PNR_SCRIPT = ""
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export_ TCL_EXTRACT_AREA_SCRIPT = "./dp/fpga_top/custom_scripts_${TECHNOLOGY}/design_compiler_${TECHNOLOGY}.tcl" # DC SCRIPT to extract area or run synthesis
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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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# Derived Or Fixed Variables
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# ***************************
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#
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# These are derived from above list variables, no need to set them explicitly
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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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export_ OPENFPGA_ENGINE_PATH = ${OPENFPGA_PATH}
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export_ TASK_DIR_NAME = ${PROJ_NAME}_task
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export_ VERILOG_PROJ_DIR = ${RELEASE_DIRECTORY}/${PROJ_NAME}_Verilog
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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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# Variable to copy files to destination
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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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export_ TAPEOUT_DIRECTORY = ${TAPEOUT_BASE}/OpenFPGA-ArcticPro3
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export_ TAPEOUT_SCRIPT = ../utils/tapeout_script.sh
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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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# Place and route related variables
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# *********************************
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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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export_ SH_PRE_INIT_DESIGN = ""
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export_ SH_POST_INIT_DESIGN = ""
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export_ SH_PRE_PLACE_OPT = ""
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export_ SH_POST_PLACE_OPT = ""
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export_ SH_PRE_CLOCK_OPT_SCRIPT = ""
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export_ SH_POST_CLOCK_OPT_SCRIPT = ""
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export_ SH_PRE_CLOCK_OPT_SCRIPT = ""
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export_ SH_POST_CLOCK_OPT_SCRIPT = ""
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export_ SH_PRE_ROUTE_AUTO_SCRIPT = ""
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export_ SH_POST_ROUTE_AUTO_SCRIPT = ""
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export_ SH_PRE_ROUTE_OPT_SCRIPT = ""
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export_ SH_POST_ROUTE_OPT_SCRIPT = ""
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export_ SH_PRE_ROUTE_OPT_SCRIPT = ""
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export_ SH_PRE_SCRIPT = ""
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export_ SH_POST_SCRIPT = ""
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export_ SH_POST_ROUTE_OPT_SCRIPT = ""
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export_ SH_PRE_ICV_IN_DESIGN_SCRIPT = ""
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export_ SH_POST_ICV_IN_DESIGN_SCRIPT = ""
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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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# FLOWVAR
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# *******
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#
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# Any variable name starting with FLOWVAR_* will be loaded in tcl scripts by default
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# and can be access with variable ${standard_cells}
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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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export_ FLOWVAR_STANDARD_CELLS = "sc_hd"
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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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# Default variables
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# *****************
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#
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# These variable has default values, typically does not require any change
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# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
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export_ DESIGN_STYLE = "hier" # Only hier supported
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export_ INIT_DESIGN_INPUT = "ASCII" # Load physical flow from DEF
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export_ RELEASE_DIRECTORY = "release"
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export_ SCRIPT_DIR = $(realpath "../../openfpga-physical/scripts") # This directory contains all the common scripts dc_utils, pt_utils, icc2_utils
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export_ DC_SCRIPT_DIR = ${SCRIPT_DIR}/dc_utils/ # Extendable variable "path1 path2"
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export_ ICC2_SCRIPT_DIR = ${SCRIPT_DIR}/icc2_utils/ # Extendable variable "path1 path2"
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export_ PT_SCRIPT_DIR = ${SCRIPT_DIR}/pt_utils/ # Extendable variable "path1 path2"
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