SOFA/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task
WRansohoff b4e3440972
Fix parsing error in FPGA1212_QLSOFA arch file.
I was pointed to this task as a starting point for generating an FPGA on the skywater PDK, and I think this small change is necessary to get the task to run with:

`python3 openfpga_flow/scripts/run_fpga_task.py FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/`
2021-02-05 11:36:29 -06:00
..
arch Fix parsing error in FPGA1212_QLSOFA arch file. 2021-02-05 11:36:29 -06:00
config [QLSOFA_HD] Updated QLSOFA_HD netlist and task 2020-12-14 13:36:52 -07:00
micro_benchmark [QLSOFA_HD] Updated QLSOFA_HD netlist and task 2020-12-14 13:36:52 -07:00
sc_verilog [QLSOFA_HD] Updated QLSOFA_HD netlist and task 2020-12-14 13:36:52 -07:00
design_variables.yml [QLSOFA_HD] Updated QLSOFA_HD netlist and task 2020-12-14 13:36:52 -07:00
generate_fabric.openfpga [QLSOFA_HD] Updated QLSOFA_HD netlist and task 2020-12-14 13:36:52 -07:00
generate_testbench.openfpga [QLSOFA_HD] Updated QLSOFA_HD netlist and task 2020-12-14 13:36:52 -07:00
process_top_def.sh [QLSOFA_HD] Updated QLSOFA_HD netlist and task 2020-12-14 13:36:52 -07:00
user_project_wrapper_empty.def [QLSOFA_HD] Updated QLSOFA_HD netlist and task 2020-12-14 13:36:52 -07:00
user_project_wrapper_template.def [QLSOFA_HD] Updated QLSOFA_HD netlist and task 2020-12-14 13:36:52 -07:00