mirror of https://github.com/lnis-uofu/SOFA.git
126 lines
4.3 KiB
Python
126 lines
4.3 KiB
Python
"""
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This file redners the fabric before the netlist generation
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"""
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import logging
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import os
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import pickle
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from glob import glob
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from pathlib import Path
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from spydrnet_physical.util import FPGAGridGen
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logger = logging.getLogger("spydrnet_logs")
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PROJ_NAME = os.environ["PROJ_NAME"]
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RELEASE_DIR = os.environ["RELEASE_DIRECTORY"]
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LAYOUT = os.environ["LAYOUT"]
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TASK_DIR_NAME = os.environ["TASK_DIR_NAME"]
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SVG_DIR = f"{RELEASE_DIR}/svg"
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XML_DIR = f"{RELEASE_DIR}/xml"
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PICKLE_DIR = f"{RELEASE_DIR}/pickle"
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def main():
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"""
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Main flow
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"""
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try:
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VPR_ARCH_FILE = glob((f"{TASK_DIR_NAME}/arch/*vpr*"))[0]
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except IndexError:
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logger.exception(
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"Architecture file not found ['%s/arch/*vpr*']", TASK_DIR_NAME)
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exit(1)
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logger.info("Reading architeture file %s", VPR_ARCH_FILE)
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# Demonstrates how to modify the structure
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fpga = FPGAGridGen(
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design_name=PROJ_NAME,
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arch_file=VPR_ARCH_FILE,
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release_root=RELEASE_DIR,
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layout=LAYOUT,
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)
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logger.info("Loading Layout %s", LAYOUT)
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fpga.enumerate_grid()
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fpga.default_parameters["cbx"][0] = 10 # uncomment to force square plan
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fpga.default_parameters["cby"][1] = 10 # uncomment to force square plan
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Path(SVG_DIR).mkdir(parents=True, exist_ok=True)
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Path(PICKLE_DIR).mkdir(parents=True, exist_ok=True)
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dwg = fpga.render_layout(
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filename=f"{SVG_DIR}/{PROJ_NAME}_render.svg", grid_io=True)
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dwg.save(pretty=True, indent=4)
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pickle.dump(dwg, open(f"{PICKLE_DIR}/{PROJ_NAME}_render.pickle", "wb"))
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dwg.save(pretty=True, indent=4)
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pickle.dump(dwg, open(f"{PICKLE_DIR}/{PROJ_NAME}_render.pickle", "wb"))
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logger.info("Saving file %s/%s_render.svg", SVG_DIR, PROJ_NAME)
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pickle.dump(fpga, open(
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f"{PICKLE_DIR}/{PROJ_NAME}_fpgagridgen_pre_tile_grid.pickle", "wb"))
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dwg = fpga.render_layout(filename="_tmp.svg", grid_io=False)
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pickle.dump(fpga, open(
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f"{PICKLE_DIR}/{PROJ_NAME}_fpgagridgen_pre_tile.pickle", "wb"))
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# ============ Modify your floorplan here ============
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# Adding stylesheet
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fpga.add_style("symbol[id*='sides_merged'] * { fill:green; opacity:0.5 }")
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fpga.add_style("symbol[id*='corner'] * { fill:#28f7c7; opacity:0.5 }")
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fpga.add_style("symbol[id*='main_tile'] * { fill:#F0A35E; opacity:0.5 }")
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fpga.add_style("symbol[id*='merged'] * { stroke:white; stroke-width:1px;}")
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# Extract width and height
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w = fpga.get_width()
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h = fpga.get_height()
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for y in range(1, h):
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x = 0
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instances = [f"cby_{x}__{y}_", f"sb_{x}__{y}_"]
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fpga.merge_symbol(instances, f"sides_merged_at_{x}_{y}")
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x = w
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instances = [f"cby_{x}__{y}_", f"sb_{x}__{y}_",
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f"cbx_{x}__{y}_", f"clb_{x}__{y}_"]
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fpga.merge_symbol(instances, f"sides_merged_at_{x}_{y}")
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for x in range(1, w):
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y = 0
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instances = [f"cbx_{x}__{y}_", f"sb_{x}__{y}_"]
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fpga.merge_symbol(instances, f"sides_merged_at_{x}_{y}")
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y = h
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instances = [f"cbx_{x}__{y}_", f"sb_{x}__{y}_",
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f"cby_{x}__{y}_", f"clb_{x}__{y}_"]
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fpga.merge_symbol(instances, f"sides_merged_at_{x}_{y}")
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# Main tile
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for x in range(1, w):
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for y in range(1, h):
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fpga.merge_symbol(
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[ f"clb_{x}__{y}_", f"sb_{x}__{y}_",
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f"cbx_{x}__{y}_", f"cby_{x}__{y}_"],
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f"main_tile_merged_{x}_{y}")
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# Corner Tiles
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fpga.merge_symbol(
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[f"cby_0__{h}_", f"sb_0__{h}_"], "corner_merged_ltop")
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fpga.merge_symbol(
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[f"cbx_{w}__{h}_", f"cby_{w}__{h}_",
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f"clb_{w}__{h}_", f"sb_{w}__{h}_"], "corner_merged_rtop")
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fpga.merge_symbol(
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[f"cbx_{w}__0_", f"cbx_{w}__1_",
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f"sb_{w}__0_", f"sb_{w}__1_",
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f"cby_{w}__1_", f"clb_{w}__1_"], "corner_merged_rbottom")
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fpga.merge_symbol(["sb_0__0_",], "corner_merged_lbottom")
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# ====================== END =========================
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dwg.saveas(
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filename=f"{SVG_DIR}/{PROJ_NAME}_restruct_render.svg", pretty=True, indent=4
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)
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pickle.dump(
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dwg, open(f"{PICKLE_DIR}/{PROJ_NAME}_restruct_render.pickle", "wb"))
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pickle.dump(fpga, open(
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f"{PICKLE_DIR}/{PROJ_NAME}_fpgagridgen.pickle", "wb"))
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logger.info("Saving file %s/%s_restruct_render.svg", SVG_DIR, PROJ_NAME)
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return dwg
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if __name__ == "__main__":
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main()
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