mirror of https://github.com/lnis-uofu/SOFA.git
83 lines
3.5 KiB
Python
83 lines
3.5 KiB
Python
#####################################################################
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# Python script to run ModelSim simulations for all the post-pnr testbenches
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# in a project directory
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# This script will
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# - Collect all the testbenches in a given directory
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# For instance:
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# ../k4_arch/pre_pnr/verilog_testbenches/and2_post_pnr_include_netlist.v
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# - Use run_post_pnr_msim_test.py to run Modelsim simulations and check results
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#####################################################################
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import os
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from os.path import dirname, abspath
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import shutil
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import re
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import argparse
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import logging
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import subprocess
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import glob
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import threading
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import multiprocessing
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import run_post_pnr_msim_test
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#####################################################################
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# Initialize logger
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#####################################################################
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logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.INFO)
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#####################################################################
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# Parse the options
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#####################################################################
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parser = argparse.ArgumentParser(description='Run a ModelSim verification task for a tape-out FPGA')
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parser.add_argument('--testbench_dir_name', required=True,
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help='Specify the directory path for the Verilog testbenches')
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parser.add_argument('--task_name', required=True,
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help='Specify the directory path for the Verilog testbenches')
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parser.add_argument('--testbench_type', default="postpnr",
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help='Specify the type of verification: postpnr|prepnr')
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args = parser.parse_args()
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#####################################################################
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# Walk through the parent directory and find all the pre-PnR testbenches
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#####################################################################
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logging.info("Finding testbenches...");
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testbench_dir_abspath = abspath(args.testbench_dir_name) + "/" + args.testbench_type + "/verilog_testbench";
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testbench_files = []
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for globbed_file in glob.glob(testbench_dir_abspath + "/*_include_netlists.v"):
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testbench_files.append(globbed_file)
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logging.info("Found " + str(len(testbench_files)) + " testbenches")
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#####################################################################
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# Try to create the directory of Modelsim projects
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#####################################################################
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parent_dir_abspath = dirname(dirname(abspath(__file__)))
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msim_task_dir_abspath = abspath(parent_dir_abspath + "/" + args.task_name) + "/" + args.testbench_type + "/verilog_testbench";
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os.makedirs(msim_task_dir_abspath, exist_ok=True)
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#####################################################################
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# Run ModelSim simulations for each testbench
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#####################################################################
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logging.info("Running Modelsim simulations...");
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num_sim_finished = 0
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msim_testrun_script_abspath = os.path.abspath(__file__)
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msim_testrun_script_abspath = re.sub(os.path.basename(msim_testrun_script_abspath), "run_post_pnr_msim_test.py", msim_testrun_script_abspath)
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threads = []
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for testbench_file in testbench_files:
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# Find testbench name
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testbench_name = re.findall("(\w+)_include_netlists.v", os.path.basename(testbench_file))[0]
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process = multiprocessing.Process(target=run_post_pnr_msim_test.run_msim, args=(testbench_file, msim_task_dir_abspath + "/" + testbench_name, testbench_name + "_autocheck_top_tb",))
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process.start()
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threads.append(process)
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for process in threads:
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process.join()
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logging.info("Done")
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logging.info("Finish " + str(len(threads)) + " ModelSim simulations")
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