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Kevin Liao f1eb4c4f88 rename module name to IO from EMBEDDED_IO_HD 2021-01-21 20:52:16 -08:00
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common rename module name to IO from EMBEDDED_IO_HD 2021-01-21 20:52:16 -08:00
README.md [Doc] Add readme for HDL directory 2020-11-03 09:23:33 -07:00

README.md

Skywater PDK

This directory contains the HDL netlists for FPGA fabrics that are automatically generated by OpenFPGA. It also includes necessary wrappers to enable the netlist generation. The custom netlists are place in the common directory.