mirror of https://github.com/lnis-uofu/SOFA.git
52 lines
1.4 KiB
Tcl
52 lines
1.4 KiB
Tcl
##########################################################
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# Template scripts to synthesize a combinational circuit
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# using Design Compiler
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# Author: Xifan Tang
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# Organization: University of Utah
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# Date: September 4th, 2020
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##########################################################
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# Variable declaration
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set CTRITICAL_PATH 1; # [ns]
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# Make sure a clean start
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remove_design -all
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set DB_FILE "/research/ece/lnis/CAD_TOOLS/DKITS/skywater/skywater-pdk/vendor/synopsys/results/lib/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
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# Read standard cell library
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# Here we consider the Skywater 130nm High Density(HD) cell library
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read_db ${DB_FILE}
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set target_library ${DB_FILE}
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set link_library ${DB_FILE}
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set DESIGN_NAME DESIGN_NAME_VAR
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set RTL_NETLIST RTL_NETLIST_VAR
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# Parse the HDL
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analyze -f verilog ${RTL_NETLIST}
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elaborate ${DESIGN_NAME}
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# Set constraints
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# Push to 0 for the minimum area
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set_max_area 0
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# Link to technology library and start compilation
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link
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compile -map_effort high
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# Output netlist
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write -format Verilog -output ../GATE_NETLISTS/${DESIGN_NAME}_post_synth.v
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# Report results
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report_unit > ../RPT/${DESIGN_NAME}_unit.rpt
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report_area > ../RPT/${DESIGN_NAME}_area.rpt
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report_timing > ../RPT/${DESIGN_NAME}_timing.rpt
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report_power > ../RPT/${DESIGN_NAME}_power.rpt
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report_reference > ../RPT/${DESIGN_NAME}_reference.rpt
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# Finish here
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exit
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