$date
	Tue Dec  8 15:56:21 2020
$end
$version
	QuestaSim Version 2019.4
$end
$timescale
	1ps
$end

$scope module fpga_top $end
$var wire 1 ! io_in [37] $end
$var wire 1 " io_in [36] $end
$var wire 1 # io_in [0] $end

$scope module fpga_core_uut $end
$var wire 1 $ scff_Wires [317] $end
$var wire 1 % scff_Wires [316] $end
$var wire 1 & scff_Wires [315] $end
$var wire 1 ' scff_Wires [314] $end
$var wire 1 ( scff_Wires [313] $end
$var wire 1 ) scff_Wires [312] $end
$var wire 1 * scff_Wires [311] $end
$var wire 1 + scff_Wires [310] $end
$var wire 1 , scff_Wires [309] $end
$var wire 1 - scff_Wires [308] $end
$var wire 1 . scff_Wires [307] $end
$var wire 1 / scff_Wires [306] $end
$var wire 1 0 scff_Wires [305] $end
$var wire 1 1 scff_Wires [304] $end
$var wire 1 2 scff_Wires [303] $end
$var wire 1 3 scff_Wires [302] $end
$var wire 1 4 scff_Wires [301] $end
$var wire 1 5 scff_Wires [300] $end
$var wire 1 6 scff_Wires [299] $end
$var wire 1 7 scff_Wires [298] $end
$var wire 1 8 scff_Wires [297] $end
$var wire 1 9 scff_Wires [296] $end
$var wire 1 : scff_Wires [295] $end
$var wire 1 ; scff_Wires [294] $end
$var wire 1 < scff_Wires [293] $end
$var wire 1 = scff_Wires [292] $end
$var wire 1 > scff_Wires [291] $end
$var wire 1 ? scff_Wires [290] $end
$var wire 1 @ scff_Wires [289] $end
$var wire 1 A scff_Wires [288] $end
$var wire 1 B scff_Wires [287] $end
$var wire 1 C scff_Wires [286] $end
$var wire 1 D scff_Wires [285] $end
$var wire 1 E scff_Wires [284] $end
$var wire 1 F scff_Wires [283] $end
$var wire 1 G scff_Wires [282] $end
$var wire 1 H scff_Wires [281] $end
$var wire 1 I scff_Wires [280] $end
$var wire 1 J scff_Wires [279] $end
$var wire 1 K scff_Wires [278] $end
$var wire 1 L scff_Wires [277] $end
$var wire 1 M scff_Wires [276] $end
$var wire 1 N scff_Wires [275] $end
$var wire 1 O scff_Wires [274] $end
$var wire 1 P scff_Wires [273] $end
$var wire 1 Q scff_Wires [272] $end
$var wire 1 R scff_Wires [271] $end
$var wire 1 S scff_Wires [270] $end
$var wire 1 T scff_Wires [269] $end
$var wire 1 U scff_Wires [268] $end
$var wire 1 V scff_Wires [267] $end
$var wire 1 W scff_Wires [266] $end
$var wire 1 X scff_Wires [265] $end
$var wire 1 Y scff_Wires [264] $end
$var wire 1 Z scff_Wires [263] $end
$var wire 1 [ scff_Wires [262] $end
$var wire 1 \ scff_Wires [261] $end
$var wire 1 ] scff_Wires [260] $end
$var wire 1 ^ scff_Wires [259] $end
$var wire 1 _ scff_Wires [258] $end
$var wire 1 ` scff_Wires [257] $end
$var wire 1 a scff_Wires [256] $end
$var wire 1 b scff_Wires [255] $end
$var wire 1 c scff_Wires [254] $end
$var wire 1 d scff_Wires [253] $end
$var wire 1 e scff_Wires [252] $end
$var wire 1 f scff_Wires [251] $end
$var wire 1 g scff_Wires [250] $end
$var wire 1 h scff_Wires [249] $end
$var wire 1 i scff_Wires [248] $end
$var wire 1 j scff_Wires [247] $end
$var wire 1 k scff_Wires [246] $end
$var wire 1 l scff_Wires [245] $end
$var wire 1 m scff_Wires [244] $end
$var wire 1 n scff_Wires [243] $end
$var wire 1 o scff_Wires [242] $end
$var wire 1 p scff_Wires [241] $end
$var wire 1 q scff_Wires [240] $end
$var wire 1 r scff_Wires [239] $end
$var wire 1 s scff_Wires [238] $end
$var wire 1 t scff_Wires [237] $end
$var wire 1 u scff_Wires [236] $end
$var wire 1 v scff_Wires [235] $end
$var wire 1 w scff_Wires [234] $end
$var wire 1 x scff_Wires [233] $end
$var wire 1 y scff_Wires [232] $end
$var wire 1 z scff_Wires [231] $end
$var wire 1 { scff_Wires [230] $end
$var wire 1 | scff_Wires [229] $end
$var wire 1 } scff_Wires [228] $end
$var wire 1 ~ scff_Wires [227] $end
$var wire 1 !! scff_Wires [226] $end
$var wire 1 "! scff_Wires [225] $end
$var wire 1 #! scff_Wires [224] $end
$var wire 1 $! scff_Wires [223] $end
$var wire 1 %! scff_Wires [222] $end
$var wire 1 &! scff_Wires [221] $end
$var wire 1 '! scff_Wires [220] $end
$var wire 1 (! scff_Wires [219] $end
$var wire 1 )! scff_Wires [218] $end
$var wire 1 *! scff_Wires [217] $end
$var wire 1 +! scff_Wires [216] $end
$var wire 1 ,! scff_Wires [215] $end
$var wire 1 -! scff_Wires [214] $end
$var wire 1 .! scff_Wires [213] $end
$var wire 1 /! scff_Wires [212] $end
$var wire 1 0! scff_Wires [211] $end
$var wire 1 1! scff_Wires [210] $end
$var wire 1 2! scff_Wires [209] $end
$var wire 1 3! scff_Wires [208] $end
$var wire 1 4! scff_Wires [207] $end
$var wire 1 5! scff_Wires [206] $end
$var wire 1 6! scff_Wires [205] $end
$var wire 1 7! scff_Wires [204] $end
$var wire 1 8! scff_Wires [203] $end
$var wire 1 9! scff_Wires [202] $end
$var wire 1 :! scff_Wires [201] $end
$var wire 1 ;! scff_Wires [200] $end
$var wire 1 <! scff_Wires [199] $end
$var wire 1 =! scff_Wires [198] $end
$var wire 1 >! scff_Wires [197] $end
$var wire 1 ?! scff_Wires [196] $end
$var wire 1 @! scff_Wires [195] $end
$var wire 1 A! scff_Wires [194] $end
$var wire 1 B! scff_Wires [193] $end
$var wire 1 C! scff_Wires [192] $end
$var wire 1 D! scff_Wires [191] $end
$var wire 1 E! scff_Wires [190] $end
$var wire 1 F! scff_Wires [189] $end
$var wire 1 G! scff_Wires [188] $end
$var wire 1 H! scff_Wires [187] $end
$var wire 1 I! scff_Wires [186] $end
$var wire 1 J! scff_Wires [185] $end
$var wire 1 K! scff_Wires [184] $end
$var wire 1 L! scff_Wires [183] $end
$var wire 1 M! scff_Wires [182] $end
$var wire 1 N! scff_Wires [181] $end
$var wire 1 O! scff_Wires [180] $end
$var wire 1 P! scff_Wires [179] $end
$var wire 1 Q! scff_Wires [178] $end
$var wire 1 R! scff_Wires [177] $end
$var wire 1 S! scff_Wires [176] $end
$var wire 1 T! scff_Wires [175] $end
$var wire 1 U! scff_Wires [174] $end
$var wire 1 V! scff_Wires [173] $end
$var wire 1 W! scff_Wires [172] $end
$var wire 1 X! scff_Wires [171] $end
$var wire 1 Y! scff_Wires [170] $end
$var wire 1 Z! scff_Wires [169] $end
$var wire 1 [! scff_Wires [168] $end
$var wire 1 \! scff_Wires [167] $end
$var wire 1 ]! scff_Wires [166] $end
$var wire 1 ^! scff_Wires [165] $end
$var wire 1 _! scff_Wires [164] $end
$var wire 1 `! scff_Wires [163] $end
$var wire 1 a! scff_Wires [162] $end
$var wire 1 b! scff_Wires [161] $end
$var wire 1 c! scff_Wires [160] $end
$var wire 1 d! scff_Wires [159] $end
$var wire 1 e! scff_Wires [158] $end
$var wire 1 f! scff_Wires [157] $end
$var wire 1 g! scff_Wires [156] $end
$var wire 1 h! scff_Wires [155] $end
$var wire 1 i! scff_Wires [154] $end
$var wire 1 j! scff_Wires [153] $end
$var wire 1 k! scff_Wires [152] $end
$var wire 1 l! scff_Wires [151] $end
$var wire 1 m! scff_Wires [150] $end
$var wire 1 n! scff_Wires [149] $end
$var wire 1 o! scff_Wires [148] $end
$var wire 1 p! scff_Wires [147] $end
$var wire 1 q! scff_Wires [146] $end
$var wire 1 r! scff_Wires [145] $end
$var wire 1 s! scff_Wires [144] $end
$var wire 1 t! scff_Wires [143] $end
$var wire 1 u! scff_Wires [142] $end
$var wire 1 v! scff_Wires [141] $end
$var wire 1 w! scff_Wires [140] $end
$var wire 1 x! scff_Wires [139] $end
$var wire 1 y! scff_Wires [138] $end
$var wire 1 z! scff_Wires [137] $end
$var wire 1 {! scff_Wires [136] $end
$var wire 1 |! scff_Wires [135] $end
$var wire 1 }! scff_Wires [134] $end
$var wire 1 ~! scff_Wires [133] $end
$var wire 1 !" scff_Wires [132] $end
$var wire 1 "" scff_Wires [131] $end
$var wire 1 #" scff_Wires [130] $end
$var wire 1 $" scff_Wires [129] $end
$var wire 1 %" scff_Wires [128] $end
$var wire 1 &" scff_Wires [127] $end
$var wire 1 '" scff_Wires [126] $end
$var wire 1 (" scff_Wires [125] $end
$var wire 1 )" scff_Wires [124] $end
$var wire 1 *" scff_Wires [123] $end
$var wire 1 +" scff_Wires [122] $end
$var wire 1 ," scff_Wires [121] $end
$var wire 1 -" scff_Wires [120] $end
$var wire 1 ." scff_Wires [119] $end
$var wire 1 /" scff_Wires [118] $end
$var wire 1 0" scff_Wires [117] $end
$var wire 1 1" scff_Wires [116] $end
$var wire 1 2" scff_Wires [115] $end
$var wire 1 3" scff_Wires [114] $end
$var wire 1 4" scff_Wires [113] $end
$var wire 1 5" scff_Wires [112] $end
$var wire 1 6" scff_Wires [111] $end
$var wire 1 7" scff_Wires [110] $end
$var wire 1 8" scff_Wires [109] $end
$var wire 1 9" scff_Wires [108] $end
$var wire 1 :" scff_Wires [107] $end
$var wire 1 ;" scff_Wires [106] $end
$var wire 1 <" scff_Wires [105] $end
$var wire 1 =" scff_Wires [104] $end
$var wire 1 >" scff_Wires [103] $end
$var wire 1 ?" scff_Wires [102] $end
$var wire 1 @" scff_Wires [101] $end
$var wire 1 A" scff_Wires [100] $end
$var wire 1 B" scff_Wires [99] $end
$var wire 1 C" scff_Wires [98] $end
$var wire 1 D" scff_Wires [97] $end
$var wire 1 E" scff_Wires [96] $end
$var wire 1 F" scff_Wires [95] $end
$var wire 1 G" scff_Wires [94] $end
$var wire 1 H" scff_Wires [93] $end
$var wire 1 I" scff_Wires [92] $end
$var wire 1 J" scff_Wires [91] $end
$var wire 1 K" scff_Wires [90] $end
$var wire 1 L" scff_Wires [89] $end
$var wire 1 M" scff_Wires [88] $end
$var wire 1 N" scff_Wires [87] $end
$var wire 1 O" scff_Wires [86] $end
$var wire 1 P" scff_Wires [85] $end
$var wire 1 Q" scff_Wires [84] $end
$var wire 1 R" scff_Wires [83] $end
$var wire 1 S" scff_Wires [82] $end
$var wire 1 T" scff_Wires [81] $end
$var wire 1 U" scff_Wires [80] $end
$var wire 1 V" scff_Wires [79] $end
$var wire 1 W" scff_Wires [78] $end
$var wire 1 X" scff_Wires [77] $end
$var wire 1 Y" scff_Wires [76] $end
$var wire 1 Z" scff_Wires [75] $end
$var wire 1 [" scff_Wires [74] $end
$var wire 1 \" scff_Wires [73] $end
$var wire 1 ]" scff_Wires [72] $end
$var wire 1 ^" scff_Wires [71] $end
$var wire 1 _" scff_Wires [70] $end
$var wire 1 `" scff_Wires [69] $end
$var wire 1 a" scff_Wires [68] $end
$var wire 1 b" scff_Wires [67] $end
$var wire 1 c" scff_Wires [66] $end
$var wire 1 d" scff_Wires [65] $end
$var wire 1 e" scff_Wires [64] $end
$var wire 1 f" scff_Wires [63] $end
$var wire 1 g" scff_Wires [62] $end
$var wire 1 h" scff_Wires [61] $end
$var wire 1 i" scff_Wires [60] $end
$var wire 1 j" scff_Wires [59] $end
$var wire 1 k" scff_Wires [58] $end
$var wire 1 l" scff_Wires [57] $end
$var wire 1 m" scff_Wires [56] $end
$var wire 1 n" scff_Wires [55] $end
$var wire 1 o" scff_Wires [54] $end
$var wire 1 p" scff_Wires [53] $end
$var wire 1 q" scff_Wires [52] $end
$var wire 1 r" scff_Wires [51] $end
$var wire 1 s" scff_Wires [50] $end
$var wire 1 t" scff_Wires [49] $end
$var wire 1 u" scff_Wires [48] $end
$var wire 1 v" scff_Wires [47] $end
$var wire 1 w" scff_Wires [46] $end
$var wire 1 x" scff_Wires [45] $end
$var wire 1 y" scff_Wires [44] $end
$var wire 1 z" scff_Wires [43] $end
$var wire 1 {" scff_Wires [42] $end
$var wire 1 |" scff_Wires [41] $end
$var wire 1 }" scff_Wires [40] $end
$var wire 1 ~" scff_Wires [39] $end
$var wire 1 !# scff_Wires [38] $end
$var wire 1 "# scff_Wires [37] $end
$var wire 1 ## scff_Wires [36] $end
$var wire 1 $# scff_Wires [35] $end
$var wire 1 %# scff_Wires [34] $end
$var wire 1 &# scff_Wires [33] $end
$var wire 1 '# scff_Wires [32] $end
$var wire 1 (# scff_Wires [31] $end
$var wire 1 )# scff_Wires [30] $end
$var wire 1 *# scff_Wires [29] $end
$var wire 1 +# scff_Wires [28] $end
$var wire 1 ,# scff_Wires [27] $end
$var wire 1 -# scff_Wires [26] $end
$var wire 1 .# scff_Wires [25] $end
$var wire 1 /# scff_Wires [24] $end
$var wire 1 0# scff_Wires [23] $end
$var wire 1 1# scff_Wires [22] $end
$var wire 1 2# scff_Wires [21] $end
$var wire 1 3# scff_Wires [20] $end
$var wire 1 4# scff_Wires [19] $end
$var wire 1 5# scff_Wires [18] $end
$var wire 1 6# scff_Wires [17] $end
$var wire 1 7# scff_Wires [16] $end
$var wire 1 8# scff_Wires [15] $end
$var wire 1 9# scff_Wires [14] $end
$var wire 1 :# scff_Wires [13] $end
$var wire 1 ;# scff_Wires [12] $end
$var wire 1 <# scff_Wires [11] $end
$var wire 1 =# scff_Wires [10] $end
$var wire 1 ># scff_Wires [9] $end
$var wire 1 ?# scff_Wires [8] $end
$var wire 1 @# scff_Wires [7] $end
$var wire 1 A# scff_Wires [6] $end
$var wire 1 B# scff_Wires [5] $end
$var wire 1 C# scff_Wires [4] $end
$var wire 1 D# scff_Wires [3] $end
$var wire 1 E# scff_Wires [2] $end
$var wire 1 F# scff_Wires [1] $end
$var wire 1 G# scff_Wires [0] $end
$var wire 1 # Test_en [0] $end

$scope module sb_0__12_ $end
$var wire 1 H# SC_IN_TOP $end
$var wire 1 G# SC_OUT_BOT $end
$upscope $end

$scope module grid_clb_1__12_ $end
$var wire 1 F# SC_IN_TOP $end
$var wire 1 E# SC_OUT_BOT $end
$upscope $end
$upscope $end
$var wire 1 I# sc_head $end
$var wire 1 J# sc_tail $end

$scope module fpga_core_uut $end

$scope module sb_12__12_ $end
$var wire 1 K# pReset [0] $end
$var wire 1 L# chany_bottom_in [0] $end
$var wire 1 M# chany_bottom_in [1] $end
$var wire 1 N# chany_bottom_in [2] $end
$var wire 1 O# chany_bottom_in [3] $end
$var wire 1 P# chany_bottom_in [4] $end
$var wire 1 Q# chany_bottom_in [5] $end
$var wire 1 R# chany_bottom_in [6] $end
$var wire 1 S# chany_bottom_in [7] $end
$var wire 1 T# chany_bottom_in [8] $end
$var wire 1 U# chany_bottom_in [9] $end
$var wire 1 V# chany_bottom_in [10] $end
$var wire 1 W# chany_bottom_in [11] $end
$var wire 1 X# chany_bottom_in [12] $end
$var wire 1 Y# chany_bottom_in [13] $end
$var wire 1 Z# chany_bottom_in [14] $end
$var wire 1 [# chany_bottom_in [15] $end
$var wire 1 \# chany_bottom_in [16] $end
$var wire 1 ]# chany_bottom_in [17] $end
$var wire 1 ^# chany_bottom_in [18] $end
$var wire 1 _# chany_bottom_in [19] $end
$var wire 1 `# chany_bottom_in [20] $end
$var wire 1 a# chany_bottom_in [21] $end
$var wire 1 b# chany_bottom_in [22] $end
$var wire 1 c# chany_bottom_in [23] $end
$var wire 1 d# chany_bottom_in [24] $end
$var wire 1 e# chany_bottom_in [25] $end
$var wire 1 f# chany_bottom_in [26] $end
$var wire 1 g# chany_bottom_in [27] $end
$var wire 1 h# chany_bottom_in [28] $end
$var wire 1 i# chany_bottom_in [29] $end
$var wire 1 j# bottom_right_grid_pin_1_ [0] $end
$var wire 1 k# bottom_left_grid_pin_44_ [0] $end
$var wire 1 l# bottom_left_grid_pin_45_ [0] $end
$var wire 1 m# bottom_left_grid_pin_46_ [0] $end
$var wire 1 n# bottom_left_grid_pin_47_ [0] $end
$var wire 1 o# bottom_left_grid_pin_48_ [0] $end
$var wire 1 p# bottom_left_grid_pin_49_ [0] $end
$var wire 1 q# bottom_left_grid_pin_50_ [0] $end
$var wire 1 r# bottom_left_grid_pin_51_ [0] $end
$var wire 1 s# chanx_left_in [0] $end
$var wire 1 t# chanx_left_in [1] $end
$var wire 1 u# chanx_left_in [2] $end
$var wire 1 v# chanx_left_in [3] $end
$var wire 1 w# chanx_left_in [4] $end
$var wire 1 x# chanx_left_in [5] $end
$var wire 1 y# chanx_left_in [6] $end
$var wire 1 z# chanx_left_in [7] $end
$var wire 1 {# chanx_left_in [8] $end
$var wire 1 |# chanx_left_in [9] $end
$var wire 1 }# chanx_left_in [10] $end
$var wire 1 ~# chanx_left_in [11] $end
$var wire 1 !$ chanx_left_in [12] $end
$var wire 1 "$ chanx_left_in [13] $end
$var wire 1 #$ chanx_left_in [14] $end
$var wire 1 $$ chanx_left_in [15] $end
$var wire 1 %$ chanx_left_in [16] $end
$var wire 1 &$ chanx_left_in [17] $end
$var wire 1 '$ chanx_left_in [18] $end
$var wire 1 ($ chanx_left_in [19] $end
$var wire 1 )$ chanx_left_in [20] $end
$var wire 1 *$ chanx_left_in [21] $end
$var wire 1 +$ chanx_left_in [22] $end
$var wire 1 ,$ chanx_left_in [23] $end
$var wire 1 -$ chanx_left_in [24] $end
$var wire 1 .$ chanx_left_in [25] $end
$var wire 1 /$ chanx_left_in [26] $end
$var wire 1 0$ chanx_left_in [27] $end
$var wire 1 1$ chanx_left_in [28] $end
$var wire 1 2$ chanx_left_in [29] $end
$var wire 1 3$ left_top_grid_pin_1_ [0] $end
$var wire 1 4$ left_bottom_grid_pin_36_ [0] $end
$var wire 1 5$ left_bottom_grid_pin_37_ [0] $end
$var wire 1 6$ left_bottom_grid_pin_38_ [0] $end
$var wire 1 7$ left_bottom_grid_pin_39_ [0] $end
$var wire 1 8$ left_bottom_grid_pin_40_ [0] $end
$var wire 1 9$ left_bottom_grid_pin_41_ [0] $end
$var wire 1 :$ left_bottom_grid_pin_42_ [0] $end
$var wire 1 ;$ left_bottom_grid_pin_43_ [0] $end
$var wire 1 <$ ccff_head [0] $end
$var wire 1 =$ chany_bottom_out [0] $end
$var wire 1 >$ chany_bottom_out [1] $end
$var wire 1 ?$ chany_bottom_out [2] $end
$var wire 1 @$ chany_bottom_out [3] $end
$var wire 1 A$ chany_bottom_out [4] $end
$var wire 1 B$ chany_bottom_out [5] $end
$var wire 1 C$ chany_bottom_out [6] $end
$var wire 1 D$ chany_bottom_out [7] $end
$var wire 1 E$ chany_bottom_out [8] $end
$var wire 1 F$ chany_bottom_out [9] $end
$var wire 1 G$ chany_bottom_out [10] $end
$var wire 1 H$ chany_bottom_out [11] $end
$var wire 1 I$ chany_bottom_out [12] $end
$var wire 1 J$ chany_bottom_out [13] $end
$var wire 1 K$ chany_bottom_out [14] $end
$var wire 1 L$ chany_bottom_out [15] $end
$var wire 1 M$ chany_bottom_out [16] $end
$var wire 1 N$ chany_bottom_out [17] $end
$var wire 1 O$ chany_bottom_out [18] $end
$var wire 1 P$ chany_bottom_out [19] $end
$var wire 1 Q$ chany_bottom_out [20] $end
$var wire 1 R$ chany_bottom_out [21] $end
$var wire 1 S$ chany_bottom_out [22] $end
$var wire 1 T$ chany_bottom_out [23] $end
$var wire 1 U$ chany_bottom_out [24] $end
$var wire 1 V$ chany_bottom_out [25] $end
$var wire 1 W$ chany_bottom_out [26] $end
$var wire 1 X$ chany_bottom_out [27] $end
$var wire 1 Y$ chany_bottom_out [28] $end
$var wire 1 Z$ chany_bottom_out [29] $end
$var wire 1 [$ chanx_left_out [0] $end
$var wire 1 \$ chanx_left_out [1] $end
$var wire 1 ]$ chanx_left_out [2] $end
$var wire 1 ^$ chanx_left_out [3] $end
$var wire 1 _$ chanx_left_out [4] $end
$var wire 1 `$ chanx_left_out [5] $end
$var wire 1 a$ chanx_left_out [6] $end
$var wire 1 b$ chanx_left_out [7] $end
$var wire 1 c$ chanx_left_out [8] $end
$var wire 1 d$ chanx_left_out [9] $end
$var wire 1 e$ chanx_left_out [10] $end
$var wire 1 f$ chanx_left_out [11] $end
$var wire 1 g$ chanx_left_out [12] $end
$var wire 1 h$ chanx_left_out [13] $end
$var wire 1 i$ chanx_left_out [14] $end
$var wire 1 j$ chanx_left_out [15] $end
$var wire 1 k$ chanx_left_out [16] $end
$var wire 1 l$ chanx_left_out [17] $end
$var wire 1 m$ chanx_left_out [18] $end
$var wire 1 n$ chanx_left_out [19] $end
$var wire 1 o$ chanx_left_out [20] $end
$var wire 1 p$ chanx_left_out [21] $end
$var wire 1 q$ chanx_left_out [22] $end
$var wire 1 r$ chanx_left_out [23] $end
$var wire 1 s$ chanx_left_out [24] $end
$var wire 1 t$ chanx_left_out [25] $end
$var wire 1 u$ chanx_left_out [26] $end
$var wire 1 v$ chanx_left_out [27] $end
$var wire 1 w$ chanx_left_out [28] $end
$var wire 1 x$ chanx_left_out [29] $end
$var wire 1 y$ ccff_tail [0] $end
$var wire 1 $ SC_IN_BOT $end
$var wire 1 z$ SC_OUT_BOT $end
$var wire 1 {$ pReset_W_in $end
$var wire 1 |$ prog_clk_0_S_in $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 ~$ prog_clk_0 $end
$var wire 1 !% mux_2level_tapbuf_size2_0_sram [0] $end
$var wire 1 "% mux_2level_tapbuf_size2_0_sram [1] $end
$var wire 1 #% mux_2level_tapbuf_size2_10_sram [0] $end
$var wire 1 $% mux_2level_tapbuf_size2_10_sram [1] $end
$var wire 1 %% mux_2level_tapbuf_size2_11_sram [0] $end
$var wire 1 &% mux_2level_tapbuf_size2_11_sram [1] $end
$var wire 1 '% mux_2level_tapbuf_size2_12_sram [0] $end
$var wire 1 (% mux_2level_tapbuf_size2_12_sram [1] $end
$var wire 1 )% mux_2level_tapbuf_size2_13_sram [0] $end
$var wire 1 *% mux_2level_tapbuf_size2_13_sram [1] $end
$var wire 1 +% mux_2level_tapbuf_size2_14_sram [0] $end
$var wire 1 ,% mux_2level_tapbuf_size2_14_sram [1] $end
$var wire 1 -% mux_2level_tapbuf_size2_15_sram [0] $end
$var wire 1 .% mux_2level_tapbuf_size2_15_sram [1] $end
$var wire 1 /% mux_2level_tapbuf_size2_16_sram [0] $end
$var wire 1 0% mux_2level_tapbuf_size2_16_sram [1] $end
$var wire 1 1% mux_2level_tapbuf_size2_17_sram [0] $end
$var wire 1 2% mux_2level_tapbuf_size2_17_sram [1] $end
$var wire 1 3% mux_2level_tapbuf_size2_18_sram [0] $end
$var wire 1 4% mux_2level_tapbuf_size2_18_sram [1] $end
$var wire 1 5% mux_2level_tapbuf_size2_19_sram [0] $end
$var wire 1 6% mux_2level_tapbuf_size2_19_sram [1] $end
$var wire 1 7% mux_2level_tapbuf_size2_1_sram [0] $end
$var wire 1 8% mux_2level_tapbuf_size2_1_sram [1] $end
$var wire 1 9% mux_2level_tapbuf_size2_20_sram [0] $end
$var wire 1 :% mux_2level_tapbuf_size2_20_sram [1] $end
$var wire 1 ;% mux_2level_tapbuf_size2_21_sram [0] $end
$var wire 1 <% mux_2level_tapbuf_size2_21_sram [1] $end
$var wire 1 =% mux_2level_tapbuf_size2_22_sram [0] $end
$var wire 1 >% mux_2level_tapbuf_size2_22_sram [1] $end
$var wire 1 ?% mux_2level_tapbuf_size2_23_sram [0] $end
$var wire 1 @% mux_2level_tapbuf_size2_23_sram [1] $end
$var wire 1 A% mux_2level_tapbuf_size2_24_sram [0] $end
$var wire 1 B% mux_2level_tapbuf_size2_24_sram [1] $end
$var wire 1 C% mux_2level_tapbuf_size2_25_sram [0] $end
$var wire 1 D% mux_2level_tapbuf_size2_25_sram [1] $end
$var wire 1 E% mux_2level_tapbuf_size2_26_sram [0] $end
$var wire 1 F% mux_2level_tapbuf_size2_26_sram [1] $end
$var wire 1 G% mux_2level_tapbuf_size2_27_sram [0] $end
$var wire 1 H% mux_2level_tapbuf_size2_27_sram [1] $end
$var wire 1 I% mux_2level_tapbuf_size2_28_sram [0] $end
$var wire 1 J% mux_2level_tapbuf_size2_28_sram [1] $end
$var wire 1 K% mux_2level_tapbuf_size2_29_sram [0] $end
$var wire 1 L% mux_2level_tapbuf_size2_29_sram [1] $end
$var wire 1 M% mux_2level_tapbuf_size2_2_sram [0] $end
$var wire 1 N% mux_2level_tapbuf_size2_2_sram [1] $end
$var wire 1 O% mux_2level_tapbuf_size2_30_sram [0] $end
$var wire 1 P% mux_2level_tapbuf_size2_30_sram [1] $end
$var wire 1 Q% mux_2level_tapbuf_size2_31_sram [0] $end
$var wire 1 R% mux_2level_tapbuf_size2_31_sram [1] $end
$var wire 1 S% mux_2level_tapbuf_size2_32_sram [0] $end
$var wire 1 T% mux_2level_tapbuf_size2_32_sram [1] $end
$var wire 1 U% mux_2level_tapbuf_size2_33_sram [0] $end
$var wire 1 V% mux_2level_tapbuf_size2_33_sram [1] $end
$var wire 1 W% mux_2level_tapbuf_size2_34_sram [0] $end
$var wire 1 X% mux_2level_tapbuf_size2_34_sram [1] $end
$var wire 1 Y% mux_2level_tapbuf_size2_35_sram [0] $end
$var wire 1 Z% mux_2level_tapbuf_size2_35_sram [1] $end
$var wire 1 [% mux_2level_tapbuf_size2_36_sram [0] $end
$var wire 1 \% mux_2level_tapbuf_size2_36_sram [1] $end
$var wire 1 ]% mux_2level_tapbuf_size2_3_sram [0] $end
$var wire 1 ^% mux_2level_tapbuf_size2_3_sram [1] $end
$var wire 1 _% mux_2level_tapbuf_size2_4_sram [0] $end
$var wire 1 `% mux_2level_tapbuf_size2_4_sram [1] $end
$var wire 1 a% mux_2level_tapbuf_size2_5_sram [0] $end
$var wire 1 b% mux_2level_tapbuf_size2_5_sram [1] $end
$var wire 1 c% mux_2level_tapbuf_size2_6_sram [0] $end
$var wire 1 d% mux_2level_tapbuf_size2_6_sram [1] $end
$var wire 1 e% mux_2level_tapbuf_size2_7_sram [0] $end
$var wire 1 f% mux_2level_tapbuf_size2_7_sram [1] $end
$var wire 1 g% mux_2level_tapbuf_size2_8_sram [0] $end
$var wire 1 h% mux_2level_tapbuf_size2_8_sram [1] $end
$var wire 1 i% mux_2level_tapbuf_size2_9_sram [0] $end
$var wire 1 j% mux_2level_tapbuf_size2_9_sram [1] $end
$var wire 1 k% mux_2level_tapbuf_size2_mem_0_ccff_tail [0] $end
$var wire 1 l% mux_2level_tapbuf_size2_mem_10_ccff_tail [0] $end
$var wire 1 m% mux_2level_tapbuf_size2_mem_11_ccff_tail [0] $end
$var wire 1 n% mux_2level_tapbuf_size2_mem_12_ccff_tail [0] $end
$var wire 1 o% mux_2level_tapbuf_size2_mem_13_ccff_tail [0] $end
$var wire 1 p% mux_2level_tapbuf_size2_mem_14_ccff_tail [0] $end
$var wire 1 q% mux_2level_tapbuf_size2_mem_15_ccff_tail [0] $end
$var wire 1 r% mux_2level_tapbuf_size2_mem_16_ccff_tail [0] $end
$var wire 1 s% mux_2level_tapbuf_size2_mem_17_ccff_tail [0] $end
$var wire 1 t% mux_2level_tapbuf_size2_mem_18_ccff_tail [0] $end
$var wire 1 u% mux_2level_tapbuf_size2_mem_19_ccff_tail [0] $end
$var wire 1 v% mux_2level_tapbuf_size2_mem_1_ccff_tail [0] $end
$var wire 1 w% mux_2level_tapbuf_size2_mem_20_ccff_tail [0] $end
$var wire 1 x% mux_2level_tapbuf_size2_mem_21_ccff_tail [0] $end
$var wire 1 y% mux_2level_tapbuf_size2_mem_22_ccff_tail [0] $end
$var wire 1 z% mux_2level_tapbuf_size2_mem_23_ccff_tail [0] $end
$var wire 1 {% mux_2level_tapbuf_size2_mem_24_ccff_tail [0] $end
$var wire 1 |% mux_2level_tapbuf_size2_mem_25_ccff_tail [0] $end
$var wire 1 }% mux_2level_tapbuf_size2_mem_26_ccff_tail [0] $end
$var wire 1 ~% mux_2level_tapbuf_size2_mem_27_ccff_tail [0] $end
$var wire 1 !& mux_2level_tapbuf_size2_mem_28_ccff_tail [0] $end
$var wire 1 "& mux_2level_tapbuf_size2_mem_29_ccff_tail [0] $end
$var wire 1 #& mux_2level_tapbuf_size2_mem_2_ccff_tail [0] $end
$var wire 1 $& mux_2level_tapbuf_size2_mem_30_ccff_tail [0] $end
$var wire 1 %& mux_2level_tapbuf_size2_mem_31_ccff_tail [0] $end
$var wire 1 && mux_2level_tapbuf_size2_mem_32_ccff_tail [0] $end
$var wire 1 '& mux_2level_tapbuf_size2_mem_33_ccff_tail [0] $end
$var wire 1 (& mux_2level_tapbuf_size2_mem_34_ccff_tail [0] $end
$var wire 1 )& mux_2level_tapbuf_size2_mem_35_ccff_tail [0] $end
$var wire 1 *& mux_2level_tapbuf_size2_mem_3_ccff_tail [0] $end
$var wire 1 +& mux_2level_tapbuf_size2_mem_4_ccff_tail [0] $end
$var wire 1 ,& mux_2level_tapbuf_size2_mem_5_ccff_tail [0] $end
$var wire 1 -& mux_2level_tapbuf_size2_mem_6_ccff_tail [0] $end
$var wire 1 .& mux_2level_tapbuf_size2_mem_7_ccff_tail [0] $end
$var wire 1 /& mux_2level_tapbuf_size2_mem_8_ccff_tail [0] $end
$var wire 1 0& mux_2level_tapbuf_size2_mem_9_ccff_tail [0] $end
$var wire 1 1& mux_2level_tapbuf_size3_0_sram [0] $end
$var wire 1 2& mux_2level_tapbuf_size3_0_sram [1] $end
$var wire 1 3& mux_2level_tapbuf_size3_1_sram [0] $end
$var wire 1 4& mux_2level_tapbuf_size3_1_sram [1] $end
$var wire 1 5& mux_2level_tapbuf_size3_2_sram [0] $end
$var wire 1 6& mux_2level_tapbuf_size3_2_sram [1] $end
$var wire 1 7& mux_2level_tapbuf_size3_3_sram [0] $end
$var wire 1 8& mux_2level_tapbuf_size3_3_sram [1] $end
$var wire 1 9& mux_2level_tapbuf_size3_mem_0_ccff_tail [0] $end
$var wire 1 :& mux_2level_tapbuf_size3_mem_1_ccff_tail [0] $end
$var wire 1 ;& mux_2level_tapbuf_size3_mem_2_ccff_tail [0] $end
$var wire 1 <& mux_2level_tapbuf_size3_mem_3_ccff_tail [0] $end
$var wire 1 =& mux_2level_tapbuf_size4_0_sram [0] $end
$var wire 1 >& mux_2level_tapbuf_size4_0_sram [1] $end
$var wire 1 ?& mux_2level_tapbuf_size4_0_sram [2] $end
$var wire 1 @& mux_2level_tapbuf_size4_0_sram [3] $end
$var wire 1 A& mux_2level_tapbuf_size4_10_sram [0] $end
$var wire 1 B& mux_2level_tapbuf_size4_10_sram [1] $end
$var wire 1 C& mux_2level_tapbuf_size4_10_sram [2] $end
$var wire 1 D& mux_2level_tapbuf_size4_10_sram [3] $end
$var wire 1 E& mux_2level_tapbuf_size4_11_sram [0] $end
$var wire 1 F& mux_2level_tapbuf_size4_11_sram [1] $end
$var wire 1 G& mux_2level_tapbuf_size4_11_sram [2] $end
$var wire 1 H& mux_2level_tapbuf_size4_11_sram [3] $end
$var wire 1 I& mux_2level_tapbuf_size4_1_sram [0] $end
$var wire 1 J& mux_2level_tapbuf_size4_1_sram [1] $end
$var wire 1 K& mux_2level_tapbuf_size4_1_sram [2] $end
$var wire 1 L& mux_2level_tapbuf_size4_1_sram [3] $end
$var wire 1 M& mux_2level_tapbuf_size4_2_sram [0] $end
$var wire 1 N& mux_2level_tapbuf_size4_2_sram [1] $end
$var wire 1 O& mux_2level_tapbuf_size4_2_sram [2] $end
$var wire 1 P& mux_2level_tapbuf_size4_2_sram [3] $end
$var wire 1 Q& mux_2level_tapbuf_size4_3_sram [0] $end
$var wire 1 R& mux_2level_tapbuf_size4_3_sram [1] $end
$var wire 1 S& mux_2level_tapbuf_size4_3_sram [2] $end
$var wire 1 T& mux_2level_tapbuf_size4_3_sram [3] $end
$var wire 1 U& mux_2level_tapbuf_size4_4_sram [0] $end
$var wire 1 V& mux_2level_tapbuf_size4_4_sram [1] $end
$var wire 1 W& mux_2level_tapbuf_size4_4_sram [2] $end
$var wire 1 X& mux_2level_tapbuf_size4_4_sram [3] $end
$var wire 1 Y& mux_2level_tapbuf_size4_5_sram [0] $end
$var wire 1 Z& mux_2level_tapbuf_size4_5_sram [1] $end
$var wire 1 [& mux_2level_tapbuf_size4_5_sram [2] $end
$var wire 1 \& mux_2level_tapbuf_size4_5_sram [3] $end
$var wire 1 ]& mux_2level_tapbuf_size4_6_sram [0] $end
$var wire 1 ^& mux_2level_tapbuf_size4_6_sram [1] $end
$var wire 1 _& mux_2level_tapbuf_size4_6_sram [2] $end
$var wire 1 `& mux_2level_tapbuf_size4_6_sram [3] $end
$var wire 1 a& mux_2level_tapbuf_size4_7_sram [0] $end
$var wire 1 b& mux_2level_tapbuf_size4_7_sram [1] $end
$var wire 1 c& mux_2level_tapbuf_size4_7_sram [2] $end
$var wire 1 d& mux_2level_tapbuf_size4_7_sram [3] $end
$var wire 1 e& mux_2level_tapbuf_size4_8_sram [0] $end
$var wire 1 f& mux_2level_tapbuf_size4_8_sram [1] $end
$var wire 1 g& mux_2level_tapbuf_size4_8_sram [2] $end
$var wire 1 h& mux_2level_tapbuf_size4_8_sram [3] $end
$var wire 1 i& mux_2level_tapbuf_size4_9_sram [0] $end
$var wire 1 j& mux_2level_tapbuf_size4_9_sram [1] $end
$var wire 1 k& mux_2level_tapbuf_size4_9_sram [2] $end
$var wire 1 l& mux_2level_tapbuf_size4_9_sram [3] $end
$var wire 1 m& mux_2level_tapbuf_size4_mem_0_ccff_tail [0] $end
$var wire 1 n& mux_2level_tapbuf_size4_mem_10_ccff_tail [0] $end
$var wire 1 o& mux_2level_tapbuf_size4_mem_11_ccff_tail [0] $end
$var wire 1 p& mux_2level_tapbuf_size4_mem_1_ccff_tail [0] $end
$var wire 1 q& mux_2level_tapbuf_size4_mem_2_ccff_tail [0] $end
$var wire 1 r& mux_2level_tapbuf_size4_mem_3_ccff_tail [0] $end
$var wire 1 s& mux_2level_tapbuf_size4_mem_4_ccff_tail [0] $end
$var wire 1 t& mux_2level_tapbuf_size4_mem_5_ccff_tail [0] $end
$var wire 1 u& mux_2level_tapbuf_size4_mem_6_ccff_tail [0] $end
$var wire 1 v& mux_2level_tapbuf_size4_mem_7_ccff_tail [0] $end
$var wire 1 w& mux_2level_tapbuf_size4_mem_8_ccff_tail [0] $end
$var wire 1 x& mux_2level_tapbuf_size4_mem_9_ccff_tail [0] $end
$var wire 1 y& SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 z& SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 {& SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 |& SYNOPSYS_UNCONNECTED_4 $end
$var wire 1 }& optlc_net_178 $end
$var wire 1 ~& SYNOPSYS_UNCONNECTED_5 $end
$var wire 1 !' SYNOPSYS_UNCONNECTED_6 $end
$var wire 1 "' SYNOPSYS_UNCONNECTED_7 $end
$var wire 1 #' SYNOPSYS_UNCONNECTED_8 $end
$var wire 1 $' SYNOPSYS_UNCONNECTED_9 $end
$var wire 1 %' SYNOPSYS_UNCONNECTED_10 $end
$var wire 1 &' SYNOPSYS_UNCONNECTED_11 $end
$var wire 1 '' SYNOPSYS_UNCONNECTED_12 $end
$var wire 1 (' optlc_net_174 $end
$var wire 1 )' SYNOPSYS_UNCONNECTED_13 $end
$var wire 1 *' SYNOPSYS_UNCONNECTED_14 $end
$var wire 1 +' SYNOPSYS_UNCONNECTED_15 $end
$var wire 1 ,' SYNOPSYS_UNCONNECTED_16 $end
$var wire 1 -' SYNOPSYS_UNCONNECTED_17 $end
$var wire 1 .' SYNOPSYS_UNCONNECTED_18 $end
$var wire 1 /' SYNOPSYS_UNCONNECTED_19 $end
$var wire 1 0' SYNOPSYS_UNCONNECTED_20 $end
$var wire 1 1' optlc_net_177 $end
$var wire 1 2' SYNOPSYS_UNCONNECTED_21 $end
$var wire 1 3' SYNOPSYS_UNCONNECTED_22 $end
$var wire 1 4' SYNOPSYS_UNCONNECTED_23 $end
$var wire 1 5' SYNOPSYS_UNCONNECTED_24 $end
$var wire 1 6' SYNOPSYS_UNCONNECTED_25 $end
$var wire 1 7' SYNOPSYS_UNCONNECTED_26 $end
$var wire 1 8' SYNOPSYS_UNCONNECTED_27 $end
$var wire 1 9' SYNOPSYS_UNCONNECTED_28 $end
$var wire 1 :' SYNOPSYS_UNCONNECTED_29 $end
$var wire 1 ;' SYNOPSYS_UNCONNECTED_30 $end
$var wire 1 <' SYNOPSYS_UNCONNECTED_31 $end
$var wire 1 =' SYNOPSYS_UNCONNECTED_32 $end
$var wire 1 >' SYNOPSYS_UNCONNECTED_33 $end
$var wire 1 ?' SYNOPSYS_UNCONNECTED_34 $end
$var wire 1 @' SYNOPSYS_UNCONNECTED_35 $end
$var wire 1 A' SYNOPSYS_UNCONNECTED_36 $end
$var wire 1 B' SYNOPSYS_UNCONNECTED_37 $end
$var wire 1 C' SYNOPSYS_UNCONNECTED_38 $end
$var wire 1 D' SYNOPSYS_UNCONNECTED_39 $end
$var wire 1 E' SYNOPSYS_UNCONNECTED_40 $end
$var wire 1 F' SYNOPSYS_UNCONNECTED_41 $end
$var wire 1 G' SYNOPSYS_UNCONNECTED_42 $end
$var wire 1 H' SYNOPSYS_UNCONNECTED_43 $end
$var wire 1 I' SYNOPSYS_UNCONNECTED_44 $end
$var wire 1 J' SYNOPSYS_UNCONNECTED_45 $end
$var wire 1 K' SYNOPSYS_UNCONNECTED_46 $end
$var wire 1 L' SYNOPSYS_UNCONNECTED_47 $end
$var wire 1 M' SYNOPSYS_UNCONNECTED_48 $end
$var wire 1 N' SYNOPSYS_UNCONNECTED_49 $end
$var wire 1 O' SYNOPSYS_UNCONNECTED_50 $end
$var wire 1 P' SYNOPSYS_UNCONNECTED_51 $end
$var wire 1 Q' SYNOPSYS_UNCONNECTED_52 $end
$var wire 1 R' optlc_net_175 $end
$var wire 1 S' SYNOPSYS_UNCONNECTED_53 $end
$var wire 1 T' SYNOPSYS_UNCONNECTED_54 $end
$var wire 1 U' SYNOPSYS_UNCONNECTED_55 $end
$var wire 1 V' SYNOPSYS_UNCONNECTED_56 $end
$var wire 1 W' SYNOPSYS_UNCONNECTED_57 $end
$var wire 1 X' SYNOPSYS_UNCONNECTED_58 $end
$var wire 1 Y' optlc_net_179 $end
$var wire 1 Z' SYNOPSYS_UNCONNECTED_59 $end
$var wire 1 [' SYNOPSYS_UNCONNECTED_60 $end
$var wire 1 \' SYNOPSYS_UNCONNECTED_61 $end
$var wire 1 ]' SYNOPSYS_UNCONNECTED_62 $end
$var wire 1 ^' SYNOPSYS_UNCONNECTED_63 $end
$var wire 1 _' SYNOPSYS_UNCONNECTED_64 $end
$var wire 1 `' SYNOPSYS_UNCONNECTED_65 $end
$var wire 1 a' SYNOPSYS_UNCONNECTED_66 $end
$var wire 1 b' SYNOPSYS_UNCONNECTED_67 $end
$var wire 1 c' SYNOPSYS_UNCONNECTED_68 $end
$var wire 1 d' SYNOPSYS_UNCONNECTED_69 $end
$var wire 1 e' SYNOPSYS_UNCONNECTED_70 $end
$var wire 1 f' SYNOPSYS_UNCONNECTED_71 $end
$var wire 1 g' SYNOPSYS_UNCONNECTED_72 $end
$var wire 1 h' SYNOPSYS_UNCONNECTED_73 $end
$var wire 1 i' SYNOPSYS_UNCONNECTED_74 $end
$var wire 1 j' SYNOPSYS_UNCONNECTED_75 $end
$var wire 1 k' SYNOPSYS_UNCONNECTED_76 $end
$var wire 1 l' SYNOPSYS_UNCONNECTED_77 $end
$var wire 1 m' SYNOPSYS_UNCONNECTED_78 $end
$var wire 1 n' SYNOPSYS_UNCONNECTED_79 $end
$var wire 1 o' SYNOPSYS_UNCONNECTED_80 $end
$var wire 1 p' optlc_net_176 $end
$var wire 1 q' SYNOPSYS_UNCONNECTED_81 $end
$var wire 1 r' SYNOPSYS_UNCONNECTED_82 $end
$var wire 1 s' SYNOPSYS_UNCONNECTED_83 $end
$var wire 1 t' SYNOPSYS_UNCONNECTED_84 $end
$var wire 1 u' SYNOPSYS_UNCONNECTED_85 $end
$var wire 1 v' SYNOPSYS_UNCONNECTED_86 $end
$var wire 1 w' SYNOPSYS_UNCONNECTED_87 $end
$var wire 1 x' SYNOPSYS_UNCONNECTED_88 $end
$var wire 1 y' SYNOPSYS_UNCONNECTED_89 $end
$var wire 1 z' SYNOPSYS_UNCONNECTED_90 $end
$var wire 1 {' SYNOPSYS_UNCONNECTED_91 $end
$var wire 1 |' SYNOPSYS_UNCONNECTED_92 $end
$var wire 1 }' SYNOPSYS_UNCONNECTED_93 $end
$var wire 1 ~' SYNOPSYS_UNCONNECTED_94 $end
$var wire 1 !( SYNOPSYS_UNCONNECTED_95 $end
$var wire 1 "( SYNOPSYS_UNCONNECTED_96 $end
$var wire 1 #( SYNOPSYS_UNCONNECTED_97 $end
$var wire 1 $( SYNOPSYS_UNCONNECTED_98 $end
$var wire 1 %( SYNOPSYS_UNCONNECTED_99 $end
$var wire 1 &( SYNOPSYS_UNCONNECTED_100 $end
$var wire 1 '( SYNOPSYS_UNCONNECTED_101 $end
$var wire 1 (( SYNOPSYS_UNCONNECTED_102 $end
$var wire 1 )( SYNOPSYS_UNCONNECTED_103 $end
$var wire 1 *( SYNOPSYS_UNCONNECTED_104 $end
$var wire 1 +( SYNOPSYS_UNCONNECTED_105 $end
$var wire 1 ,( SYNOPSYS_UNCONNECTED_106 $end
$var wire 1 -( SYNOPSYS_UNCONNECTED_107 $end
$var wire 1 .( SYNOPSYS_UNCONNECTED_108 $end
$var wire 1 /( SYNOPSYS_UNCONNECTED_109 $end
$var wire 1 0( SYNOPSYS_UNCONNECTED_110 $end
$var wire 1 1( SYNOPSYS_UNCONNECTED_111 $end
$var wire 1 2( SYNOPSYS_UNCONNECTED_112 $end
$var wire 1 3( SYNOPSYS_UNCONNECTED_113 $end
$var wire 1 4( SYNOPSYS_UNCONNECTED_114 $end
$var wire 1 5( SYNOPSYS_UNCONNECTED_115 $end
$var wire 1 6( SYNOPSYS_UNCONNECTED_116 $end
$var wire 1 7( SYNOPSYS_UNCONNECTED_117 $end
$var wire 1 8( SYNOPSYS_UNCONNECTED_118 $end
$var wire 1 9( SYNOPSYS_UNCONNECTED_119 $end
$var wire 1 :( SYNOPSYS_UNCONNECTED_120 $end
$var wire 1 ;( SYNOPSYS_UNCONNECTED_121 $end
$var wire 1 <( SYNOPSYS_UNCONNECTED_122 $end
$var wire 1 =( SYNOPSYS_UNCONNECTED_123 $end
$var wire 1 >( SYNOPSYS_UNCONNECTED_124 $end
$var wire 1 ?( SYNOPSYS_UNCONNECTED_125 $end
$var wire 1 @( SYNOPSYS_UNCONNECTED_126 $end
$var wire 1 A( SYNOPSYS_UNCONNECTED_127 $end
$var wire 1 B( SYNOPSYS_UNCONNECTED_128 $end
$var wire 1 C( SYNOPSYS_UNCONNECTED_129 $end
$var wire 1 D( SYNOPSYS_UNCONNECTED_130 $end
$var wire 1 E( SYNOPSYS_UNCONNECTED_131 $end
$var wire 1 F( SYNOPSYS_UNCONNECTED_132 $end
$var wire 1 G( SYNOPSYS_UNCONNECTED_133 $end
$var wire 1 H( SYNOPSYS_UNCONNECTED_134 $end
$var wire 1 I( SYNOPSYS_UNCONNECTED_135 $end
$var wire 1 J( SYNOPSYS_UNCONNECTED_136 $end

$scope module mux_bottom_track_1 $end
$var wire 1 j# in [0] $end
$var wire 1 m# in [1] $end
$var wire 1 p# in [2] $end
$var wire 1 t# in [3] $end
$var wire 1 =& sram [0] $end
$var wire 1 >& sram [1] $end
$var wire 1 ?& sram [2] $end
$var wire 1 @& sram [3] $end
$var wire 1 y& sram_inv [0] $end
$var wire 1 z& sram_inv [1] $end
$var wire 1 {& sram_inv [2] $end
$var wire 1 |& sram_inv [3] $end
$var wire 1 =$ out [0] $end
$var wire 1 }& p0 $end
$var wire 1 K( local_encoder2to3_0_data [0] $end
$var wire 1 L( local_encoder2to3_0_data [1] $end
$var wire 1 M( local_encoder2to3_0_data [2] $end
$var wire 1 N( local_encoder2to3_0_data_inv [0] $end
$var wire 1 O( local_encoder2to3_0_data_inv [1] $end
$var wire 1 P( local_encoder2to3_0_data_inv [2] $end
$var wire 1 Q( local_encoder2to3_1_data [0] $end
$var wire 1 R( local_encoder2to3_1_data [1] $end
$var wire 1 S( local_encoder2to3_1_data [2] $end
$var wire 1 T( local_encoder2to3_1_data_inv [0] $end
$var wire 1 U( local_encoder2to3_1_data_inv [1] $end
$var wire 1 V( local_encoder2to3_1_data_inv [2] $end
$var wire 1 W( mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end
$var wire 1 X( mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end
$var wire 1 Y( SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 Z( BUF_net_86 $end

$scope module local_encoder2to3_0_ $end
$var wire 1 =& addr [0] $end
$var wire 1 >& addr [1] $end
$var wire 1 K( data [0] $end
$var wire 1 L( data [1] $end
$var wire 1 M( data [2] $end
$var wire 1 N( data_inv [0] $end
$var wire 1 O( data_inv [1] $end
$var wire 1 P( data_inv [2] $end

$scope module U8 $end
$var wire 1 N( Y $end
$var wire 1 K( A $end
$var supply1 1 [( VPWR $end
$var supply0 1 \( VGND $end
$var supply1 1 ]( VPB $end
$var supply0 1 ^( VNB $end

$scope module base $end
$var wire 1 N( Y $end
$var wire 1 K( A $end
$var wire 1 _( not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 L( Y $end
$var wire 1 O( A $end
$var supply1 1 `( VPWR $end
$var supply0 1 a( VGND $end
$var supply1 1 b( VPB $end
$var supply0 1 c( VNB $end

$scope module base $end
$var wire 1 L( Y $end
$var wire 1 O( A $end
$var wire 1 d( not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 O( Y $end
$var wire 1 =& A $end
$var wire 1 P( B $end
$var supply1 1 e( VPWR $end
$var supply0 1 f( VGND $end
$var supply1 1 g( VPB $end
$var supply0 1 h( VNB $end

$scope module base $end
$var wire 1 O( Y $end
$var wire 1 =& A $end
$var wire 1 P( B $end
$var wire 1 i( nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 P( Y $end
$var wire 1 M( A $end
$var supply1 1 j( VPWR $end
$var supply0 1 k( VGND $end
$var supply1 1 l( VPB $end
$var supply0 1 m( VNB $end

$scope module base $end
$var wire 1 P( Y $end
$var wire 1 M( A $end
$var wire 1 n( not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 K( Y $end
$var wire 1 M( A $end
$var wire 1 =& B $end
$var supply1 1 o( VPWR $end
$var supply0 1 p( VGND $end
$var supply1 1 q( VPB $end
$var supply0 1 r( VNB $end

$scope module base $end
$var wire 1 K( Y $end
$var wire 1 M( A $end
$var wire 1 =& B $end
$var wire 1 s( nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_1__0 $end
$var wire 1 M( X $end
$var wire 1 >& A $end
$var supply1 1 t( VPWR $end
$var supply0 1 u( VGND $end
$var supply1 1 v( VPB $end
$var supply0 1 w( VNB $end

$scope module base $end
$var wire 1 M( X $end
$var wire 1 >& A $end
$var wire 1 x( buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module local_encoder2to3_1_ $end
$var wire 1 ?& addr [0] $end
$var wire 1 @& addr [1] $end
$var wire 1 Q( data [0] $end
$var wire 1 R( data [1] $end
$var wire 1 S( data [2] $end
$var wire 1 T( data_inv [0] $end
$var wire 1 U( data_inv [1] $end
$var wire 1 V( data_inv [2] $end

$scope module U8 $end
$var wire 1 T( Y $end
$var wire 1 Q( A $end
$var supply1 1 y( VPWR $end
$var supply0 1 z( VGND $end
$var supply1 1 {( VPB $end
$var supply0 1 |( VNB $end

$scope module base $end
$var wire 1 T( Y $end
$var wire 1 Q( A $end
$var wire 1 }( not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 R( Y $end
$var wire 1 U( A $end
$var supply1 1 ~( VPWR $end
$var supply0 1 !) VGND $end
$var supply1 1 ") VPB $end
$var supply0 1 #) VNB $end

$scope module base $end
$var wire 1 R( Y $end
$var wire 1 U( A $end
$var wire 1 $) not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 U( Y $end
$var wire 1 ?& A $end
$var wire 1 V( B $end
$var supply1 1 %) VPWR $end
$var supply0 1 &) VGND $end
$var supply1 1 ') VPB $end
$var supply0 1 () VNB $end

$scope module base $end
$var wire 1 U( Y $end
$var wire 1 ?& A $end
$var wire 1 V( B $end
$var wire 1 )) nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 V( Y $end
$var wire 1 S( A $end
$var supply1 1 *) VPWR $end
$var supply0 1 +) VGND $end
$var supply1 1 ,) VPB $end
$var supply0 1 -) VNB $end

$scope module base $end
$var wire 1 V( Y $end
$var wire 1 S( A $end
$var wire 1 .) not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 Q( Y $end
$var wire 1 S( A $end
$var wire 1 ?& B $end
$var supply1 1 /) VPWR $end
$var supply0 1 0) VGND $end
$var supply1 1 1) VPB $end
$var supply0 1 2) VNB $end

$scope module base $end
$var wire 1 Q( Y $end
$var wire 1 S( A $end
$var wire 1 ?& B $end
$var wire 1 3) nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_2__1 $end
$var wire 1 S( X $end
$var wire 1 @& A $end
$var supply1 1 4) VPWR $end
$var supply0 1 5) VGND $end
$var supply1 1 6) VPB $end
$var supply0 1 7) VNB $end

$scope module base $end
$var wire 1 S( X $end
$var wire 1 @& A $end
$var wire 1 8) buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 j# in [0] $end
$var wire 1 m# in [1] $end
$var wire 1 p# in [2] $end
$var wire 1 K( mem [0] $end
$var wire 1 L( mem [1] $end
$var wire 1 M( mem [2] $end
$var wire 1 N( mem_inv [0] $end
$var wire 1 O( mem_inv [1] $end
$var wire 1 P( mem_inv [2] $end
$var wire 1 W( out [0] $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 W( Z $end
$var wire 1 j# Q1 $end
$var wire 1 m# Q2 $end
$var wire 1 p# Q3 $end
$var wire 1 K( S0 $end
$var wire 1 N( S0B $end
$var wire 1 L( S1 $end
$var wire 1 O( S1B $end
$var wire 1 M( S2 $end
$var wire 1 P( S2B $end
$var wire 1 9) Q1__bar $end
$var wire 1 :) Q2__bar $end
$var wire 1 ;) Q3__bar $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 W( in [0] $end
$var wire 1 t# in [1] $end
$var wire 1 Y( in [2] $end
$var wire 1 Q( mem [0] $end
$var wire 1 R( mem [1] $end
$var wire 1 S( mem [2] $end
$var wire 1 T( mem_inv [0] $end
$var wire 1 U( mem_inv [1] $end
$var wire 1 V( mem_inv [2] $end
$var wire 1 X( out [0] $end
$var wire 1 }& p0 $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 X( Z $end
$var wire 1 W( Q1 $end
$var wire 1 t# Q2 $end
$var wire 1 }& Q3 $end
$var wire 1 Q( S0 $end
$var wire 1 T( S0B $end
$var wire 1 R( S1 $end
$var wire 1 U( S1B $end
$var wire 1 S( S2 $end
$var wire 1 V( S2B $end
$var wire 1 <) Q1__bar $end
$var wire 1 =) Q2__bar $end
$var wire 1 >) Q3__bar $end
$upscope $end
$upscope $end

$scope module BINV_R_85 $end
$var wire 1 =$ Y $end
$var wire 1 Z( A $end
$var supply1 1 ?) VPWR $end
$var supply0 1 @) VGND $end
$var supply1 1 A) VPB $end
$var supply0 1 B) VNB $end

$scope module base $end
$var wire 1 =$ Y $end
$var wire 1 Z( A $end
$var wire 1 C) not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_86 $end
$var wire 1 Z( Y $end
$var wire 1 X( A $end
$var supply1 1 D) VPWR $end
$var supply0 1 E) VGND $end
$var supply1 1 F) VPB $end
$var supply0 1 G) VNB $end

$scope module base $end
$var wire 1 Z( Y $end
$var wire 1 X( A $end
$var wire 1 H) not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_3 $end
$var wire 1 k# in [0] $end
$var wire 1 n# in [1] $end
$var wire 1 q# in [2] $end
$var wire 1 u# in [3] $end
$var wire 1 I& sram [0] $end
$var wire 1 J& sram [1] $end
$var wire 1 K& sram [2] $end
$var wire 1 L& sram [3] $end
$var wire 1 ~& sram_inv [0] $end
$var wire 1 !' sram_inv [1] $end
$var wire 1 "' sram_inv [2] $end
$var wire 1 #' sram_inv [3] $end
$var wire 1 >$ out [0] $end
$var wire 1 }& p0 $end
$var wire 1 I) local_encoder2to3_0_data [0] $end
$var wire 1 J) local_encoder2to3_0_data [1] $end
$var wire 1 K) local_encoder2to3_0_data [2] $end
$var wire 1 L) local_encoder2to3_0_data_inv [0] $end
$var wire 1 M) local_encoder2to3_0_data_inv [1] $end
$var wire 1 N) local_encoder2to3_0_data_inv [2] $end
$var wire 1 O) local_encoder2to3_1_data [0] $end
$var wire 1 P) local_encoder2to3_1_data [1] $end
$var wire 1 Q) local_encoder2to3_1_data [2] $end
$var wire 1 R) local_encoder2to3_1_data_inv [0] $end
$var wire 1 S) local_encoder2to3_1_data_inv [1] $end
$var wire 1 T) local_encoder2to3_1_data_inv [2] $end
$var wire 1 U) mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end
$var wire 1 V) mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end
$var wire 1 W) SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 X) BUF_net_88 $end

$scope module local_encoder2to3_0_ $end
$var wire 1 I& addr [0] $end
$var wire 1 J& addr [1] $end
$var wire 1 I) data [0] $end
$var wire 1 J) data [1] $end
$var wire 1 K) data [2] $end
$var wire 1 L) data_inv [0] $end
$var wire 1 M) data_inv [1] $end
$var wire 1 N) data_inv [2] $end

$scope module U8 $end
$var wire 1 L) Y $end
$var wire 1 I) A $end
$var supply1 1 Y) VPWR $end
$var supply0 1 Z) VGND $end
$var supply1 1 [) VPB $end
$var supply0 1 \) VNB $end

$scope module base $end
$var wire 1 L) Y $end
$var wire 1 I) A $end
$var wire 1 ]) not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 J) Y $end
$var wire 1 M) A $end
$var supply1 1 ^) VPWR $end
$var supply0 1 _) VGND $end
$var supply1 1 `) VPB $end
$var supply0 1 a) VNB $end

$scope module base $end
$var wire 1 J) Y $end
$var wire 1 M) A $end
$var wire 1 b) not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 M) Y $end
$var wire 1 I& A $end
$var wire 1 N) B $end
$var supply1 1 c) VPWR $end
$var supply0 1 d) VGND $end
$var supply1 1 e) VPB $end
$var supply0 1 f) VNB $end

$scope module base $end
$var wire 1 M) Y $end
$var wire 1 I& A $end
$var wire 1 N) B $end
$var wire 1 g) nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 N) Y $end
$var wire 1 K) A $end
$var supply1 1 h) VPWR $end
$var supply0 1 i) VGND $end
$var supply1 1 j) VPB $end
$var supply0 1 k) VNB $end

$scope module base $end
$var wire 1 N) Y $end
$var wire 1 K) A $end
$var wire 1 l) not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 I) Y $end
$var wire 1 K) A $end
$var wire 1 I& B $end
$var supply1 1 m) VPWR $end
$var supply0 1 n) VGND $end
$var supply1 1 o) VPB $end
$var supply0 1 p) VNB $end

$scope module base $end
$var wire 1 I) Y $end
$var wire 1 K) A $end
$var wire 1 I& B $end
$var wire 1 q) nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_3__2 $end
$var wire 1 K) X $end
$var wire 1 J& A $end
$var supply1 1 r) VPWR $end
$var supply0 1 s) VGND $end
$var supply1 1 t) VPB $end
$var supply0 1 u) VNB $end

$scope module base $end
$var wire 1 K) X $end
$var wire 1 J& A $end
$var wire 1 v) buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module local_encoder2to3_1_ $end
$var wire 1 K& addr [0] $end
$var wire 1 L& addr [1] $end
$var wire 1 O) data [0] $end
$var wire 1 P) data [1] $end
$var wire 1 Q) data [2] $end
$var wire 1 R) data_inv [0] $end
$var wire 1 S) data_inv [1] $end
$var wire 1 T) data_inv [2] $end

$scope module U8 $end
$var wire 1 R) Y $end
$var wire 1 O) A $end
$var supply1 1 w) VPWR $end
$var supply0 1 x) VGND $end
$var supply1 1 y) VPB $end
$var supply0 1 z) VNB $end

$scope module base $end
$var wire 1 R) Y $end
$var wire 1 O) A $end
$var wire 1 {) not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 P) Y $end
$var wire 1 S) A $end
$var supply1 1 |) VPWR $end
$var supply0 1 }) VGND $end
$var supply1 1 ~) VPB $end
$var supply0 1 !* VNB $end

$scope module base $end
$var wire 1 P) Y $end
$var wire 1 S) A $end
$var wire 1 "* not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 S) Y $end
$var wire 1 K& A $end
$var wire 1 T) B $end
$var supply1 1 #* VPWR $end
$var supply0 1 $* VGND $end
$var supply1 1 %* VPB $end
$var supply0 1 &* VNB $end

$scope module base $end
$var wire 1 S) Y $end
$var wire 1 K& A $end
$var wire 1 T) B $end
$var wire 1 '* nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 T) Y $end
$var wire 1 Q) A $end
$var supply1 1 (* VPWR $end
$var supply0 1 )* VGND $end
$var supply1 1 ** VPB $end
$var supply0 1 +* VNB $end

$scope module base $end
$var wire 1 T) Y $end
$var wire 1 Q) A $end
$var wire 1 ,* not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 O) Y $end
$var wire 1 Q) A $end
$var wire 1 K& B $end
$var supply1 1 -* VPWR $end
$var supply0 1 .* VGND $end
$var supply1 1 /* VPB $end
$var supply0 1 0* VNB $end

$scope module base $end
$var wire 1 O) Y $end
$var wire 1 Q) A $end
$var wire 1 K& B $end
$var wire 1 1* nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_4__3 $end
$var wire 1 Q) X $end
$var wire 1 L& A $end
$var supply1 1 2* VPWR $end
$var supply0 1 3* VGND $end
$var supply1 1 4* VPB $end
$var supply0 1 5* VNB $end

$scope module base $end
$var wire 1 Q) X $end
$var wire 1 L& A $end
$var wire 1 6* buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 k# in [0] $end
$var wire 1 n# in [1] $end
$var wire 1 q# in [2] $end
$var wire 1 I) mem [0] $end
$var wire 1 J) mem [1] $end
$var wire 1 K) mem [2] $end
$var wire 1 L) mem_inv [0] $end
$var wire 1 M) mem_inv [1] $end
$var wire 1 N) mem_inv [2] $end
$var wire 1 U) out [0] $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 U) Z $end
$var wire 1 k# Q1 $end
$var wire 1 n# Q2 $end
$var wire 1 q# Q3 $end
$var wire 1 I) S0 $end
$var wire 1 L) S0B $end
$var wire 1 J) S1 $end
$var wire 1 M) S1B $end
$var wire 1 K) S2 $end
$var wire 1 N) S2B $end
$var wire 1 7* Q1__bar $end
$var wire 1 8* Q2__bar $end
$var wire 1 9* Q3__bar $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 U) in [0] $end
$var wire 1 u# in [1] $end
$var wire 1 W) in [2] $end
$var wire 1 O) mem [0] $end
$var wire 1 P) mem [1] $end
$var wire 1 Q) mem [2] $end
$var wire 1 R) mem_inv [0] $end
$var wire 1 S) mem_inv [1] $end
$var wire 1 T) mem_inv [2] $end
$var wire 1 V) out [0] $end
$var wire 1 }& p0 $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 V) Z $end
$var wire 1 U) Q1 $end
$var wire 1 u# Q2 $end
$var wire 1 }& Q3 $end
$var wire 1 O) S0 $end
$var wire 1 R) S0B $end
$var wire 1 P) S1 $end
$var wire 1 S) S1B $end
$var wire 1 Q) S2 $end
$var wire 1 T) S2B $end
$var wire 1 :* Q1__bar $end
$var wire 1 ;* Q2__bar $end
$var wire 1 <* Q3__bar $end
$upscope $end
$upscope $end

$scope module BINV_R_87 $end
$var wire 1 >$ Y $end
$var wire 1 X) A $end
$var supply1 1 =* VPWR $end
$var supply0 1 >* VGND $end
$var supply1 1 ?* VPB $end
$var supply0 1 @* VNB $end

$scope module base $end
$var wire 1 >$ Y $end
$var wire 1 X) A $end
$var wire 1 A* not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_88 $end
$var wire 1 X) Y $end
$var wire 1 V) A $end
$var supply1 1 B* VPWR $end
$var supply0 1 C* VGND $end
$var supply1 1 D* VPB $end
$var supply0 1 E* VNB $end

$scope module base $end
$var wire 1 X) Y $end
$var wire 1 V) A $end
$var wire 1 F* not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_5 $end
$var wire 1 l# in [0] $end
$var wire 1 o# in [1] $end
$var wire 1 r# in [2] $end
$var wire 1 v# in [3] $end
$var wire 1 M& sram [0] $end
$var wire 1 N& sram [1] $end
$var wire 1 O& sram [2] $end
$var wire 1 P& sram [3] $end
$var wire 1 $' sram_inv [0] $end
$var wire 1 %' sram_inv [1] $end
$var wire 1 &' sram_inv [2] $end
$var wire 1 '' sram_inv [3] $end
$var wire 1 ?$ out [0] $end
$var wire 1 (' p0 $end
$var wire 1 G* local_encoder2to3_0_data [0] $end
$var wire 1 H* local_encoder2to3_0_data [1] $end
$var wire 1 I* local_encoder2to3_0_data [2] $end
$var wire 1 J* local_encoder2to3_0_data_inv [0] $end
$var wire 1 K* local_encoder2to3_0_data_inv [1] $end
$var wire 1 L* local_encoder2to3_0_data_inv [2] $end
$var wire 1 M* local_encoder2to3_1_data [0] $end
$var wire 1 N* local_encoder2to3_1_data [1] $end
$var wire 1 O* local_encoder2to3_1_data [2] $end
$var wire 1 P* local_encoder2to3_1_data_inv [0] $end
$var wire 1 Q* local_encoder2to3_1_data_inv [1] $end
$var wire 1 R* local_encoder2to3_1_data_inv [2] $end
$var wire 1 S* mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end
$var wire 1 T* mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end
$var wire 1 U* SYNOPSYS_UNCONNECTED_1 $end

$scope module local_encoder2to3_0_ $end
$var wire 1 M& addr [0] $end
$var wire 1 N& addr [1] $end
$var wire 1 G* data [0] $end
$var wire 1 H* data [1] $end
$var wire 1 I* data [2] $end
$var wire 1 J* data_inv [0] $end
$var wire 1 K* data_inv [1] $end
$var wire 1 L* data_inv [2] $end

$scope module U8 $end
$var wire 1 J* Y $end
$var wire 1 G* A $end
$var supply1 1 V* VPWR $end
$var supply0 1 W* VGND $end
$var supply1 1 X* VPB $end
$var supply0 1 Y* VNB $end

$scope module base $end
$var wire 1 J* Y $end
$var wire 1 G* A $end
$var wire 1 Z* not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 H* Y $end
$var wire 1 K* A $end
$var supply1 1 [* VPWR $end
$var supply0 1 \* VGND $end
$var supply1 1 ]* VPB $end
$var supply0 1 ^* VNB $end

$scope module base $end
$var wire 1 H* Y $end
$var wire 1 K* A $end
$var wire 1 _* not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 K* Y $end
$var wire 1 M& A $end
$var wire 1 L* B $end
$var supply1 1 `* VPWR $end
$var supply0 1 a* VGND $end
$var supply1 1 b* VPB $end
$var supply0 1 c* VNB $end

$scope module base $end
$var wire 1 K* Y $end
$var wire 1 M& A $end
$var wire 1 L* B $end
$var wire 1 d* nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 L* Y $end
$var wire 1 I* A $end
$var supply1 1 e* VPWR $end
$var supply0 1 f* VGND $end
$var supply1 1 g* VPB $end
$var supply0 1 h* VNB $end

$scope module base $end
$var wire 1 L* Y $end
$var wire 1 I* A $end
$var wire 1 i* not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 G* Y $end
$var wire 1 I* A $end
$var wire 1 M& B $end
$var supply1 1 j* VPWR $end
$var supply0 1 k* VGND $end
$var supply1 1 l* VPB $end
$var supply0 1 m* VNB $end

$scope module base $end
$var wire 1 G* Y $end
$var wire 1 I* A $end
$var wire 1 M& B $end
$var wire 1 n* nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_5__4 $end
$var wire 1 I* X $end
$var wire 1 N& A $end
$var supply1 1 o* VPWR $end
$var supply0 1 p* VGND $end
$var supply1 1 q* VPB $end
$var supply0 1 r* VNB $end

$scope module base $end
$var wire 1 I* X $end
$var wire 1 N& A $end
$var wire 1 s* buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module local_encoder2to3_1_ $end
$var wire 1 O& addr [0] $end
$var wire 1 P& addr [1] $end
$var wire 1 M* data [0] $end
$var wire 1 N* data [1] $end
$var wire 1 O* data [2] $end
$var wire 1 P* data_inv [0] $end
$var wire 1 Q* data_inv [1] $end
$var wire 1 R* data_inv [2] $end

$scope module U8 $end
$var wire 1 P* Y $end
$var wire 1 M* A $end
$var supply1 1 t* VPWR $end
$var supply0 1 u* VGND $end
$var supply1 1 v* VPB $end
$var supply0 1 w* VNB $end

$scope module base $end
$var wire 1 P* Y $end
$var wire 1 M* A $end
$var wire 1 x* not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 N* Y $end
$var wire 1 Q* A $end
$var supply1 1 y* VPWR $end
$var supply0 1 z* VGND $end
$var supply1 1 {* VPB $end
$var supply0 1 |* VNB $end

$scope module base $end
$var wire 1 N* Y $end
$var wire 1 Q* A $end
$var wire 1 }* not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 Q* Y $end
$var wire 1 O& A $end
$var wire 1 R* B $end
$var supply1 1 ~* VPWR $end
$var supply0 1 !+ VGND $end
$var supply1 1 "+ VPB $end
$var supply0 1 #+ VNB $end

$scope module base $end
$var wire 1 Q* Y $end
$var wire 1 O& A $end
$var wire 1 R* B $end
$var wire 1 $+ nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 R* Y $end
$var wire 1 O* A $end
$var supply1 1 %+ VPWR $end
$var supply0 1 &+ VGND $end
$var supply1 1 '+ VPB $end
$var supply0 1 (+ VNB $end

$scope module base $end
$var wire 1 R* Y $end
$var wire 1 O* A $end
$var wire 1 )+ not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 M* Y $end
$var wire 1 O* A $end
$var wire 1 O& B $end
$var supply1 1 *+ VPWR $end
$var supply0 1 ++ VGND $end
$var supply1 1 ,+ VPB $end
$var supply0 1 -+ VNB $end

$scope module base $end
$var wire 1 M* Y $end
$var wire 1 O* A $end
$var wire 1 O& B $end
$var wire 1 .+ nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_6__5 $end
$var wire 1 O* X $end
$var wire 1 P& A $end
$var supply1 1 /+ VPWR $end
$var supply0 1 0+ VGND $end
$var supply1 1 1+ VPB $end
$var supply0 1 2+ VNB $end

$scope module base $end
$var wire 1 O* X $end
$var wire 1 P& A $end
$var wire 1 3+ buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 l# in [0] $end
$var wire 1 o# in [1] $end
$var wire 1 r# in [2] $end
$var wire 1 G* mem [0] $end
$var wire 1 H* mem [1] $end
$var wire 1 I* mem [2] $end
$var wire 1 J* mem_inv [0] $end
$var wire 1 K* mem_inv [1] $end
$var wire 1 L* mem_inv [2] $end
$var wire 1 S* out [0] $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 S* Z $end
$var wire 1 l# Q1 $end
$var wire 1 o# Q2 $end
$var wire 1 r# Q3 $end
$var wire 1 G* S0 $end
$var wire 1 J* S0B $end
$var wire 1 H* S1 $end
$var wire 1 K* S1B $end
$var wire 1 I* S2 $end
$var wire 1 L* S2B $end
$var wire 1 4+ Q1__bar $end
$var wire 1 5+ Q2__bar $end
$var wire 1 6+ Q3__bar $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 S* in [0] $end
$var wire 1 v# in [1] $end
$var wire 1 U* in [2] $end
$var wire 1 M* mem [0] $end
$var wire 1 N* mem [1] $end
$var wire 1 O* mem [2] $end
$var wire 1 P* mem_inv [0] $end
$var wire 1 Q* mem_inv [1] $end
$var wire 1 R* mem_inv [2] $end
$var wire 1 T* out [0] $end
$var wire 1 (' p0 $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 T* Z $end
$var wire 1 S* Q1 $end
$var wire 1 v# Q2 $end
$var wire 1 (' Q3 $end
$var wire 1 M* S0 $end
$var wire 1 P* S0B $end
$var wire 1 N* S1 $end
$var wire 1 Q* S1B $end
$var wire 1 O* S2 $end
$var wire 1 R* S2B $end
$var wire 1 7+ Q1__bar $end
$var wire 1 8+ Q2__bar $end
$var wire 1 9+ Q3__bar $end
$upscope $end
$upscope $end

$scope module BUFT_RR_89 $end
$var wire 1 ?$ X $end
$var wire 1 T* A $end
$var supply1 1 :+ VPWR $end
$var supply0 1 ;+ VGND $end
$var supply1 1 <+ VPB $end
$var supply0 1 =+ VNB $end

$scope module base $end
$var wire 1 ?$ X $end
$var wire 1 T* A $end
$var wire 1 >+ buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_7 $end
$var wire 1 j# in [0] $end
$var wire 1 m# in [1] $end
$var wire 1 p# in [2] $end
$var wire 1 w# in [3] $end
$var wire 1 Q& sram [0] $end
$var wire 1 R& sram [1] $end
$var wire 1 S& sram [2] $end
$var wire 1 T& sram [3] $end
$var wire 1 )' sram_inv [0] $end
$var wire 1 *' sram_inv [1] $end
$var wire 1 +' sram_inv [2] $end
$var wire 1 ,' sram_inv [3] $end
$var wire 1 @$ out [0] $end
$var wire 1 }& p0 $end
$var wire 1 ?+ local_encoder2to3_0_data [0] $end
$var wire 1 @+ local_encoder2to3_0_data [1] $end
$var wire 1 A+ local_encoder2to3_0_data [2] $end
$var wire 1 B+ local_encoder2to3_0_data_inv [0] $end
$var wire 1 C+ local_encoder2to3_0_data_inv [1] $end
$var wire 1 D+ local_encoder2to3_0_data_inv [2] $end
$var wire 1 E+ local_encoder2to3_1_data [0] $end
$var wire 1 F+ local_encoder2to3_1_data [1] $end
$var wire 1 G+ local_encoder2to3_1_data [2] $end
$var wire 1 H+ local_encoder2to3_1_data_inv [0] $end
$var wire 1 I+ local_encoder2to3_1_data_inv [1] $end
$var wire 1 J+ local_encoder2to3_1_data_inv [2] $end
$var wire 1 K+ mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end
$var wire 1 L+ mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end
$var wire 1 M+ SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 N+ BUF_net_91 $end

$scope module local_encoder2to3_0_ $end
$var wire 1 Q& addr [0] $end
$var wire 1 R& addr [1] $end
$var wire 1 ?+ data [0] $end
$var wire 1 @+ data [1] $end
$var wire 1 A+ data [2] $end
$var wire 1 B+ data_inv [0] $end
$var wire 1 C+ data_inv [1] $end
$var wire 1 D+ data_inv [2] $end

$scope module U8 $end
$var wire 1 B+ Y $end
$var wire 1 ?+ A $end
$var supply1 1 O+ VPWR $end
$var supply0 1 P+ VGND $end
$var supply1 1 Q+ VPB $end
$var supply0 1 R+ VNB $end

$scope module base $end
$var wire 1 B+ Y $end
$var wire 1 ?+ A $end
$var wire 1 S+ not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 @+ Y $end
$var wire 1 C+ A $end
$var supply1 1 T+ VPWR $end
$var supply0 1 U+ VGND $end
$var supply1 1 V+ VPB $end
$var supply0 1 W+ VNB $end

$scope module base $end
$var wire 1 @+ Y $end
$var wire 1 C+ A $end
$var wire 1 X+ not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 C+ Y $end
$var wire 1 Q& A $end
$var wire 1 D+ B $end
$var supply1 1 Y+ VPWR $end
$var supply0 1 Z+ VGND $end
$var supply1 1 [+ VPB $end
$var supply0 1 \+ VNB $end

$scope module base $end
$var wire 1 C+ Y $end
$var wire 1 Q& A $end
$var wire 1 D+ B $end
$var wire 1 ]+ nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 D+ Y $end
$var wire 1 A+ A $end
$var supply1 1 ^+ VPWR $end
$var supply0 1 _+ VGND $end
$var supply1 1 `+ VPB $end
$var supply0 1 a+ VNB $end

$scope module base $end
$var wire 1 D+ Y $end
$var wire 1 A+ A $end
$var wire 1 b+ not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 ?+ Y $end
$var wire 1 A+ A $end
$var wire 1 Q& B $end
$var supply1 1 c+ VPWR $end
$var supply0 1 d+ VGND $end
$var supply1 1 e+ VPB $end
$var supply0 1 f+ VNB $end

$scope module base $end
$var wire 1 ?+ Y $end
$var wire 1 A+ A $end
$var wire 1 Q& B $end
$var wire 1 g+ nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_7__6 $end
$var wire 1 A+ X $end
$var wire 1 R& A $end
$var supply1 1 h+ VPWR $end
$var supply0 1 i+ VGND $end
$var supply1 1 j+ VPB $end
$var supply0 1 k+ VNB $end

$scope module base $end
$var wire 1 A+ X $end
$var wire 1 R& A $end
$var wire 1 l+ buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module local_encoder2to3_1_ $end
$var wire 1 S& addr [0] $end
$var wire 1 T& addr [1] $end
$var wire 1 E+ data [0] $end
$var wire 1 F+ data [1] $end
$var wire 1 G+ data [2] $end
$var wire 1 H+ data_inv [0] $end
$var wire 1 I+ data_inv [1] $end
$var wire 1 J+ data_inv [2] $end

$scope module U8 $end
$var wire 1 H+ Y $end
$var wire 1 E+ A $end
$var supply1 1 m+ VPWR $end
$var supply0 1 n+ VGND $end
$var supply1 1 o+ VPB $end
$var supply0 1 p+ VNB $end

$scope module base $end
$var wire 1 H+ Y $end
$var wire 1 E+ A $end
$var wire 1 q+ not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 F+ Y $end
$var wire 1 I+ A $end
$var supply1 1 r+ VPWR $end
$var supply0 1 s+ VGND $end
$var supply1 1 t+ VPB $end
$var supply0 1 u+ VNB $end

$scope module base $end
$var wire 1 F+ Y $end
$var wire 1 I+ A $end
$var wire 1 v+ not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 I+ Y $end
$var wire 1 S& A $end
$var wire 1 J+ B $end
$var supply1 1 w+ VPWR $end
$var supply0 1 x+ VGND $end
$var supply1 1 y+ VPB $end
$var supply0 1 z+ VNB $end

$scope module base $end
$var wire 1 I+ Y $end
$var wire 1 S& A $end
$var wire 1 J+ B $end
$var wire 1 {+ nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 J+ Y $end
$var wire 1 G+ A $end
$var supply1 1 |+ VPWR $end
$var supply0 1 }+ VGND $end
$var supply1 1 ~+ VPB $end
$var supply0 1 !, VNB $end

$scope module base $end
$var wire 1 J+ Y $end
$var wire 1 G+ A $end
$var wire 1 ", not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 E+ Y $end
$var wire 1 G+ A $end
$var wire 1 S& B $end
$var supply1 1 #, VPWR $end
$var supply0 1 $, VGND $end
$var supply1 1 %, VPB $end
$var supply0 1 &, VNB $end

$scope module base $end
$var wire 1 E+ Y $end
$var wire 1 G+ A $end
$var wire 1 S& B $end
$var wire 1 ', nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_8__7 $end
$var wire 1 G+ X $end
$var wire 1 T& A $end
$var supply1 1 (, VPWR $end
$var supply0 1 ), VGND $end
$var supply1 1 *, VPB $end
$var supply0 1 +, VNB $end

$scope module base $end
$var wire 1 G+ X $end
$var wire 1 T& A $end
$var wire 1 ,, buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 j# in [0] $end
$var wire 1 m# in [1] $end
$var wire 1 p# in [2] $end
$var wire 1 ?+ mem [0] $end
$var wire 1 @+ mem [1] $end
$var wire 1 A+ mem [2] $end
$var wire 1 B+ mem_inv [0] $end
$var wire 1 C+ mem_inv [1] $end
$var wire 1 D+ mem_inv [2] $end
$var wire 1 K+ out [0] $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 K+ Z $end
$var wire 1 j# Q1 $end
$var wire 1 m# Q2 $end
$var wire 1 p# Q3 $end
$var wire 1 ?+ S0 $end
$var wire 1 B+ S0B $end
$var wire 1 @+ S1 $end
$var wire 1 C+ S1B $end
$var wire 1 A+ S2 $end
$var wire 1 D+ S2B $end
$var wire 1 -, Q1__bar $end
$var wire 1 ., Q2__bar $end
$var wire 1 /, Q3__bar $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 K+ in [0] $end
$var wire 1 w# in [1] $end
$var wire 1 M+ in [2] $end
$var wire 1 E+ mem [0] $end
$var wire 1 F+ mem [1] $end
$var wire 1 G+ mem [2] $end
$var wire 1 H+ mem_inv [0] $end
$var wire 1 I+ mem_inv [1] $end
$var wire 1 J+ mem_inv [2] $end
$var wire 1 L+ out [0] $end
$var wire 1 }& p0 $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 L+ Z $end
$var wire 1 K+ Q1 $end
$var wire 1 w# Q2 $end
$var wire 1 }& Q3 $end
$var wire 1 E+ S0 $end
$var wire 1 H+ S0B $end
$var wire 1 F+ S1 $end
$var wire 1 I+ S1B $end
$var wire 1 G+ S2 $end
$var wire 1 J+ S2B $end
$var wire 1 0, Q1__bar $end
$var wire 1 1, Q2__bar $end
$var wire 1 2, Q3__bar $end
$upscope $end
$upscope $end

$scope module BINV_R_90 $end
$var wire 1 @$ Y $end
$var wire 1 N+ A $end
$var supply1 1 3, VPWR $end
$var supply0 1 4, VGND $end
$var supply1 1 5, VPB $end
$var supply0 1 6, VNB $end

$scope module base $end
$var wire 1 @$ Y $end
$var wire 1 N+ A $end
$var wire 1 7, not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_91 $end
$var wire 1 N+ Y $end
$var wire 1 L+ A $end
$var supply1 1 8, VPWR $end
$var supply0 1 9, VGND $end
$var supply1 1 :, VPB $end
$var supply0 1 ;, VNB $end

$scope module base $end
$var wire 1 N+ Y $end
$var wire 1 L+ A $end
$var wire 1 <, not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_9 $end
$var wire 1 k# in [0] $end
$var wire 1 n# in [1] $end
$var wire 1 q# in [2] $end
$var wire 1 x# in [3] $end
$var wire 1 U& sram [0] $end
$var wire 1 V& sram [1] $end
$var wire 1 W& sram [2] $end
$var wire 1 X& sram [3] $end
$var wire 1 -' sram_inv [0] $end
$var wire 1 .' sram_inv [1] $end
$var wire 1 /' sram_inv [2] $end
$var wire 1 0' sram_inv [3] $end
$var wire 1 A$ out [0] $end
$var wire 1 1' p0 $end
$var wire 1 =, local_encoder2to3_0_data [0] $end
$var wire 1 >, local_encoder2to3_0_data [1] $end
$var wire 1 ?, local_encoder2to3_0_data [2] $end
$var wire 1 @, local_encoder2to3_0_data_inv [0] $end
$var wire 1 A, local_encoder2to3_0_data_inv [1] $end
$var wire 1 B, local_encoder2to3_0_data_inv [2] $end
$var wire 1 C, local_encoder2to3_1_data [0] $end
$var wire 1 D, local_encoder2to3_1_data [1] $end
$var wire 1 E, local_encoder2to3_1_data [2] $end
$var wire 1 F, local_encoder2to3_1_data_inv [0] $end
$var wire 1 G, local_encoder2to3_1_data_inv [1] $end
$var wire 1 H, local_encoder2to3_1_data_inv [2] $end
$var wire 1 I, mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end
$var wire 1 J, mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end
$var wire 1 K, SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 L, BUF_net_93 $end

$scope module local_encoder2to3_0_ $end
$var wire 1 U& addr [0] $end
$var wire 1 V& addr [1] $end
$var wire 1 =, data [0] $end
$var wire 1 >, data [1] $end
$var wire 1 ?, data [2] $end
$var wire 1 @, data_inv [0] $end
$var wire 1 A, data_inv [1] $end
$var wire 1 B, data_inv [2] $end

$scope module U8 $end
$var wire 1 @, Y $end
$var wire 1 =, A $end
$var supply1 1 M, VPWR $end
$var supply0 1 N, VGND $end
$var supply1 1 O, VPB $end
$var supply0 1 P, VNB $end

$scope module base $end
$var wire 1 @, Y $end
$var wire 1 =, A $end
$var wire 1 Q, not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 >, Y $end
$var wire 1 A, A $end
$var supply1 1 R, VPWR $end
$var supply0 1 S, VGND $end
$var supply1 1 T, VPB $end
$var supply0 1 U, VNB $end

$scope module base $end
$var wire 1 >, Y $end
$var wire 1 A, A $end
$var wire 1 V, not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 A, Y $end
$var wire 1 U& A $end
$var wire 1 B, B $end
$var supply1 1 W, VPWR $end
$var supply0 1 X, VGND $end
$var supply1 1 Y, VPB $end
$var supply0 1 Z, VNB $end

$scope module base $end
$var wire 1 A, Y $end
$var wire 1 U& A $end
$var wire 1 B, B $end
$var wire 1 [, nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 B, Y $end
$var wire 1 ?, A $end
$var supply1 1 \, VPWR $end
$var supply0 1 ], VGND $end
$var supply1 1 ^, VPB $end
$var supply0 1 _, VNB $end

$scope module base $end
$var wire 1 B, Y $end
$var wire 1 ?, A $end
$var wire 1 `, not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 =, Y $end
$var wire 1 ?, A $end
$var wire 1 U& B $end
$var supply1 1 a, VPWR $end
$var supply0 1 b, VGND $end
$var supply1 1 c, VPB $end
$var supply0 1 d, VNB $end

$scope module base $end
$var wire 1 =, Y $end
$var wire 1 ?, A $end
$var wire 1 U& B $end
$var wire 1 e, nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_9__8 $end
$var wire 1 ?, X $end
$var wire 1 V& A $end
$var supply1 1 f, VPWR $end
$var supply0 1 g, VGND $end
$var supply1 1 h, VPB $end
$var supply0 1 i, VNB $end

$scope module base $end
$var wire 1 ?, X $end
$var wire 1 V& A $end
$var wire 1 j, buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module local_encoder2to3_1_ $end
$var wire 1 W& addr [0] $end
$var wire 1 X& addr [1] $end
$var wire 1 C, data [0] $end
$var wire 1 D, data [1] $end
$var wire 1 E, data [2] $end
$var wire 1 F, data_inv [0] $end
$var wire 1 G, data_inv [1] $end
$var wire 1 H, data_inv [2] $end

$scope module U8 $end
$var wire 1 F, Y $end
$var wire 1 C, A $end
$var supply1 1 k, VPWR $end
$var supply0 1 l, VGND $end
$var supply1 1 m, VPB $end
$var supply0 1 n, VNB $end

$scope module base $end
$var wire 1 F, Y $end
$var wire 1 C, A $end
$var wire 1 o, not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 D, Y $end
$var wire 1 G, A $end
$var supply1 1 p, VPWR $end
$var supply0 1 q, VGND $end
$var supply1 1 r, VPB $end
$var supply0 1 s, VNB $end

$scope module base $end
$var wire 1 D, Y $end
$var wire 1 G, A $end
$var wire 1 t, not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 G, Y $end
$var wire 1 W& A $end
$var wire 1 H, B $end
$var supply1 1 u, VPWR $end
$var supply0 1 v, VGND $end
$var supply1 1 w, VPB $end
$var supply0 1 x, VNB $end

$scope module base $end
$var wire 1 G, Y $end
$var wire 1 W& A $end
$var wire 1 H, B $end
$var wire 1 y, nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 H, Y $end
$var wire 1 E, A $end
$var supply1 1 z, VPWR $end
$var supply0 1 {, VGND $end
$var supply1 1 |, VPB $end
$var supply0 1 }, VNB $end

$scope module base $end
$var wire 1 H, Y $end
$var wire 1 E, A $end
$var wire 1 ~, not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 C, Y $end
$var wire 1 E, A $end
$var wire 1 W& B $end
$var supply1 1 !- VPWR $end
$var supply0 1 "- VGND $end
$var supply1 1 #- VPB $end
$var supply0 1 $- VNB $end

$scope module base $end
$var wire 1 C, Y $end
$var wire 1 E, A $end
$var wire 1 W& B $end
$var wire 1 %- nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_10__9 $end
$var wire 1 E, X $end
$var wire 1 X& A $end
$var supply1 1 &- VPWR $end
$var supply0 1 '- VGND $end
$var supply1 1 (- VPB $end
$var supply0 1 )- VNB $end

$scope module base $end
$var wire 1 E, X $end
$var wire 1 X& A $end
$var wire 1 *- buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 k# in [0] $end
$var wire 1 n# in [1] $end
$var wire 1 q# in [2] $end
$var wire 1 =, mem [0] $end
$var wire 1 >, mem [1] $end
$var wire 1 ?, mem [2] $end
$var wire 1 @, mem_inv [0] $end
$var wire 1 A, mem_inv [1] $end
$var wire 1 B, mem_inv [2] $end
$var wire 1 I, out [0] $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 I, Z $end
$var wire 1 k# Q1 $end
$var wire 1 n# Q2 $end
$var wire 1 q# Q3 $end
$var wire 1 =, S0 $end
$var wire 1 @, S0B $end
$var wire 1 >, S1 $end
$var wire 1 A, S1B $end
$var wire 1 ?, S2 $end
$var wire 1 B, S2B $end
$var wire 1 +- Q1__bar $end
$var wire 1 ,- Q2__bar $end
$var wire 1 -- Q3__bar $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 I, in [0] $end
$var wire 1 x# in [1] $end
$var wire 1 K, in [2] $end
$var wire 1 C, mem [0] $end
$var wire 1 D, mem [1] $end
$var wire 1 E, mem [2] $end
$var wire 1 F, mem_inv [0] $end
$var wire 1 G, mem_inv [1] $end
$var wire 1 H, mem_inv [2] $end
$var wire 1 J, out [0] $end
$var wire 1 1' p0 $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 J, Z $end
$var wire 1 I, Q1 $end
$var wire 1 x# Q2 $end
$var wire 1 1' Q3 $end
$var wire 1 C, S0 $end
$var wire 1 F, S0B $end
$var wire 1 D, S1 $end
$var wire 1 G, S1B $end
$var wire 1 E, S2 $end
$var wire 1 H, S2B $end
$var wire 1 .- Q1__bar $end
$var wire 1 /- Q2__bar $end
$var wire 1 0- Q3__bar $end
$upscope $end
$upscope $end

$scope module BINV_R_92 $end
$var wire 1 A$ Y $end
$var wire 1 L, A $end
$var supply1 1 1- VPWR $end
$var supply0 1 2- VGND $end
$var supply1 1 3- VPB $end
$var supply0 1 4- VNB $end

$scope module base $end
$var wire 1 A$ Y $end
$var wire 1 L, A $end
$var wire 1 5- not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_93 $end
$var wire 1 L, Y $end
$var wire 1 J, A $end
$var supply1 1 6- VPWR $end
$var supply0 1 7- VGND $end
$var supply1 1 8- VPB $end
$var supply0 1 9- VNB $end

$scope module base $end
$var wire 1 L, Y $end
$var wire 1 J, A $end
$var wire 1 :- not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_11 $end
$var wire 1 l# in [0] $end
$var wire 1 o# in [1] $end
$var wire 1 r# in [2] $end
$var wire 1 y# in [3] $end
$var wire 1 Y& sram [0] $end
$var wire 1 Z& sram [1] $end
$var wire 1 [& sram [2] $end
$var wire 1 \& sram [3] $end
$var wire 1 2' sram_inv [0] $end
$var wire 1 3' sram_inv [1] $end
$var wire 1 4' sram_inv [2] $end
$var wire 1 5' sram_inv [3] $end
$var wire 1 B$ out [0] $end
$var wire 1 (' p0 $end
$var wire 1 ;- local_encoder2to3_0_data [0] $end
$var wire 1 <- local_encoder2to3_0_data [1] $end
$var wire 1 =- local_encoder2to3_0_data [2] $end
$var wire 1 >- local_encoder2to3_0_data_inv [0] $end
$var wire 1 ?- local_encoder2to3_0_data_inv [1] $end
$var wire 1 @- local_encoder2to3_0_data_inv [2] $end
$var wire 1 A- local_encoder2to3_1_data [0] $end
$var wire 1 B- local_encoder2to3_1_data [1] $end
$var wire 1 C- local_encoder2to3_1_data [2] $end
$var wire 1 D- local_encoder2to3_1_data_inv [0] $end
$var wire 1 E- local_encoder2to3_1_data_inv [1] $end
$var wire 1 F- local_encoder2to3_1_data_inv [2] $end
$var wire 1 G- mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end
$var wire 1 H- mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end
$var wire 1 I- SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 J- BUF_net_95 $end

$scope module local_encoder2to3_0_ $end
$var wire 1 Y& addr [0] $end
$var wire 1 Z& addr [1] $end
$var wire 1 ;- data [0] $end
$var wire 1 <- data [1] $end
$var wire 1 =- data [2] $end
$var wire 1 >- data_inv [0] $end
$var wire 1 ?- data_inv [1] $end
$var wire 1 @- data_inv [2] $end

$scope module U8 $end
$var wire 1 >- Y $end
$var wire 1 ;- A $end
$var supply1 1 K- VPWR $end
$var supply0 1 L- VGND $end
$var supply1 1 M- VPB $end
$var supply0 1 N- VNB $end

$scope module base $end
$var wire 1 >- Y $end
$var wire 1 ;- A $end
$var wire 1 O- not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 <- Y $end
$var wire 1 ?- A $end
$var supply1 1 P- VPWR $end
$var supply0 1 Q- VGND $end
$var supply1 1 R- VPB $end
$var supply0 1 S- VNB $end

$scope module base $end
$var wire 1 <- Y $end
$var wire 1 ?- A $end
$var wire 1 T- not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 ?- Y $end
$var wire 1 Y& A $end
$var wire 1 @- B $end
$var supply1 1 U- VPWR $end
$var supply0 1 V- VGND $end
$var supply1 1 W- VPB $end
$var supply0 1 X- VNB $end

$scope module base $end
$var wire 1 ?- Y $end
$var wire 1 Y& A $end
$var wire 1 @- B $end
$var wire 1 Y- nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 @- Y $end
$var wire 1 =- A $end
$var supply1 1 Z- VPWR $end
$var supply0 1 [- VGND $end
$var supply1 1 \- VPB $end
$var supply0 1 ]- VNB $end

$scope module base $end
$var wire 1 @- Y $end
$var wire 1 =- A $end
$var wire 1 ^- not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 ;- Y $end
$var wire 1 =- A $end
$var wire 1 Y& B $end
$var supply1 1 _- VPWR $end
$var supply0 1 `- VGND $end
$var supply1 1 a- VPB $end
$var supply0 1 b- VNB $end

$scope module base $end
$var wire 1 ;- Y $end
$var wire 1 =- A $end
$var wire 1 Y& B $end
$var wire 1 c- nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_11__10 $end
$var wire 1 =- X $end
$var wire 1 Z& A $end
$var supply1 1 d- VPWR $end
$var supply0 1 e- VGND $end
$var supply1 1 f- VPB $end
$var supply0 1 g- VNB $end

$scope module base $end
$var wire 1 =- X $end
$var wire 1 Z& A $end
$var wire 1 h- buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module local_encoder2to3_1_ $end
$var wire 1 [& addr [0] $end
$var wire 1 \& addr [1] $end
$var wire 1 A- data [0] $end
$var wire 1 B- data [1] $end
$var wire 1 C- data [2] $end
$var wire 1 D- data_inv [0] $end
$var wire 1 E- data_inv [1] $end
$var wire 1 F- data_inv [2] $end

$scope module U8 $end
$var wire 1 D- Y $end
$var wire 1 A- A $end
$var supply1 1 i- VPWR $end
$var supply0 1 j- VGND $end
$var supply1 1 k- VPB $end
$var supply0 1 l- VNB $end

$scope module base $end
$var wire 1 D- Y $end
$var wire 1 A- A $end
$var wire 1 m- not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 B- Y $end
$var wire 1 E- A $end
$var supply1 1 n- VPWR $end
$var supply0 1 o- VGND $end
$var supply1 1 p- VPB $end
$var supply0 1 q- VNB $end

$scope module base $end
$var wire 1 B- Y $end
$var wire 1 E- A $end
$var wire 1 r- not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 E- Y $end
$var wire 1 [& A $end
$var wire 1 F- B $end
$var supply1 1 s- VPWR $end
$var supply0 1 t- VGND $end
$var supply1 1 u- VPB $end
$var supply0 1 v- VNB $end

$scope module base $end
$var wire 1 E- Y $end
$var wire 1 [& A $end
$var wire 1 F- B $end
$var wire 1 w- nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 F- Y $end
$var wire 1 C- A $end
$var supply1 1 x- VPWR $end
$var supply0 1 y- VGND $end
$var supply1 1 z- VPB $end
$var supply0 1 {- VNB $end

$scope module base $end
$var wire 1 F- Y $end
$var wire 1 C- A $end
$var wire 1 |- not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 A- Y $end
$var wire 1 C- A $end
$var wire 1 [& B $end
$var supply1 1 }- VPWR $end
$var supply0 1 ~- VGND $end
$var supply1 1 !. VPB $end
$var supply0 1 ". VNB $end

$scope module base $end
$var wire 1 A- Y $end
$var wire 1 C- A $end
$var wire 1 [& B $end
$var wire 1 #. nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_12__11 $end
$var wire 1 C- X $end
$var wire 1 \& A $end
$var supply1 1 $. VPWR $end
$var supply0 1 %. VGND $end
$var supply1 1 &. VPB $end
$var supply0 1 '. VNB $end

$scope module base $end
$var wire 1 C- X $end
$var wire 1 \& A $end
$var wire 1 (. buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 l# in [0] $end
$var wire 1 o# in [1] $end
$var wire 1 r# in [2] $end
$var wire 1 ;- mem [0] $end
$var wire 1 <- mem [1] $end
$var wire 1 =- mem [2] $end
$var wire 1 >- mem_inv [0] $end
$var wire 1 ?- mem_inv [1] $end
$var wire 1 @- mem_inv [2] $end
$var wire 1 G- out [0] $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 G- Z $end
$var wire 1 l# Q1 $end
$var wire 1 o# Q2 $end
$var wire 1 r# Q3 $end
$var wire 1 ;- S0 $end
$var wire 1 >- S0B $end
$var wire 1 <- S1 $end
$var wire 1 ?- S1B $end
$var wire 1 =- S2 $end
$var wire 1 @- S2B $end
$var wire 1 ). Q1__bar $end
$var wire 1 *. Q2__bar $end
$var wire 1 +. Q3__bar $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 G- in [0] $end
$var wire 1 y# in [1] $end
$var wire 1 I- in [2] $end
$var wire 1 A- mem [0] $end
$var wire 1 B- mem [1] $end
$var wire 1 C- mem [2] $end
$var wire 1 D- mem_inv [0] $end
$var wire 1 E- mem_inv [1] $end
$var wire 1 F- mem_inv [2] $end
$var wire 1 H- out [0] $end
$var wire 1 (' p0 $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 H- Z $end
$var wire 1 G- Q1 $end
$var wire 1 y# Q2 $end
$var wire 1 (' Q3 $end
$var wire 1 A- S0 $end
$var wire 1 D- S0B $end
$var wire 1 B- S1 $end
$var wire 1 E- S1B $end
$var wire 1 C- S2 $end
$var wire 1 F- S2B $end
$var wire 1 ,. Q1__bar $end
$var wire 1 -. Q2__bar $end
$var wire 1 .. Q3__bar $end
$upscope $end
$upscope $end

$scope module BINV_R_94 $end
$var wire 1 B$ Y $end
$var wire 1 J- A $end
$var supply1 1 /. VPWR $end
$var supply0 1 0. VGND $end
$var supply1 1 1. VPB $end
$var supply0 1 2. VNB $end

$scope module base $end
$var wire 1 B$ Y $end
$var wire 1 J- A $end
$var wire 1 3. not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_95 $end
$var wire 1 J- Y $end
$var wire 1 H- A $end
$var supply1 1 4. VPWR $end
$var supply0 1 5. VGND $end
$var supply1 1 6. VPB $end
$var supply0 1 7. VNB $end

$scope module base $end
$var wire 1 J- Y $end
$var wire 1 H- A $end
$var wire 1 8. not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_1 $end
$var wire 1 i# in [0] $end
$var wire 1 3$ in [1] $end
$var wire 1 6$ in [2] $end
$var wire 1 9$ in [3] $end
$var wire 1 ]& sram [0] $end
$var wire 1 ^& sram [1] $end
$var wire 1 _& sram [2] $end
$var wire 1 `& sram [3] $end
$var wire 1 6' sram_inv [0] $end
$var wire 1 7' sram_inv [1] $end
$var wire 1 8' sram_inv [2] $end
$var wire 1 9' sram_inv [3] $end
$var wire 1 [$ out [0] $end
$var wire 1 (' p0 $end
$var wire 1 9. local_encoder2to3_0_data [0] $end
$var wire 1 :. local_encoder2to3_0_data [1] $end
$var wire 1 ;. local_encoder2to3_0_data [2] $end
$var wire 1 <. local_encoder2to3_0_data_inv [0] $end
$var wire 1 =. local_encoder2to3_0_data_inv [1] $end
$var wire 1 >. local_encoder2to3_0_data_inv [2] $end
$var wire 1 ?. local_encoder2to3_1_data [0] $end
$var wire 1 @. local_encoder2to3_1_data [1] $end
$var wire 1 A. local_encoder2to3_1_data [2] $end
$var wire 1 B. local_encoder2to3_1_data_inv [0] $end
$var wire 1 C. local_encoder2to3_1_data_inv [1] $end
$var wire 1 D. local_encoder2to3_1_data_inv [2] $end
$var wire 1 E. mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end
$var wire 1 F. mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end
$var wire 1 G. SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 H. BUF_net_97 $end

$scope module local_encoder2to3_0_ $end
$var wire 1 ]& addr [0] $end
$var wire 1 ^& addr [1] $end
$var wire 1 9. data [0] $end
$var wire 1 :. data [1] $end
$var wire 1 ;. data [2] $end
$var wire 1 <. data_inv [0] $end
$var wire 1 =. data_inv [1] $end
$var wire 1 >. data_inv [2] $end

$scope module U8 $end
$var wire 1 <. Y $end
$var wire 1 9. A $end
$var supply1 1 I. VPWR $end
$var supply0 1 J. VGND $end
$var supply1 1 K. VPB $end
$var supply0 1 L. VNB $end

$scope module base $end
$var wire 1 <. Y $end
$var wire 1 9. A $end
$var wire 1 M. not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 :. Y $end
$var wire 1 =. A $end
$var supply1 1 N. VPWR $end
$var supply0 1 O. VGND $end
$var supply1 1 P. VPB $end
$var supply0 1 Q. VNB $end

$scope module base $end
$var wire 1 :. Y $end
$var wire 1 =. A $end
$var wire 1 R. not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 =. Y $end
$var wire 1 ]& A $end
$var wire 1 >. B $end
$var supply1 1 S. VPWR $end
$var supply0 1 T. VGND $end
$var supply1 1 U. VPB $end
$var supply0 1 V. VNB $end

$scope module base $end
$var wire 1 =. Y $end
$var wire 1 ]& A $end
$var wire 1 >. B $end
$var wire 1 W. nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 >. Y $end
$var wire 1 ;. A $end
$var supply1 1 X. VPWR $end
$var supply0 1 Y. VGND $end
$var supply1 1 Z. VPB $end
$var supply0 1 [. VNB $end

$scope module base $end
$var wire 1 >. Y $end
$var wire 1 ;. A $end
$var wire 1 \. not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 9. Y $end
$var wire 1 ;. A $end
$var wire 1 ]& B $end
$var supply1 1 ]. VPWR $end
$var supply0 1 ^. VGND $end
$var supply1 1 _. VPB $end
$var supply0 1 `. VNB $end

$scope module base $end
$var wire 1 9. Y $end
$var wire 1 ;. A $end
$var wire 1 ]& B $end
$var wire 1 a. nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_13__12 $end
$var wire 1 ;. X $end
$var wire 1 ^& A $end
$var supply1 1 b. VPWR $end
$var supply0 1 c. VGND $end
$var supply1 1 d. VPB $end
$var supply0 1 e. VNB $end

$scope module base $end
$var wire 1 ;. X $end
$var wire 1 ^& A $end
$var wire 1 f. buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module local_encoder2to3_1_ $end
$var wire 1 _& addr [0] $end
$var wire 1 `& addr [1] $end
$var wire 1 ?. data [0] $end
$var wire 1 @. data [1] $end
$var wire 1 A. data [2] $end
$var wire 1 B. data_inv [0] $end
$var wire 1 C. data_inv [1] $end
$var wire 1 D. data_inv [2] $end

$scope module U8 $end
$var wire 1 B. Y $end
$var wire 1 ?. A $end
$var supply1 1 g. VPWR $end
$var supply0 1 h. VGND $end
$var supply1 1 i. VPB $end
$var supply0 1 j. VNB $end

$scope module base $end
$var wire 1 B. Y $end
$var wire 1 ?. A $end
$var wire 1 k. not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 @. Y $end
$var wire 1 C. A $end
$var supply1 1 l. VPWR $end
$var supply0 1 m. VGND $end
$var supply1 1 n. VPB $end
$var supply0 1 o. VNB $end

$scope module base $end
$var wire 1 @. Y $end
$var wire 1 C. A $end
$var wire 1 p. not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 C. Y $end
$var wire 1 _& A $end
$var wire 1 D. B $end
$var supply1 1 q. VPWR $end
$var supply0 1 r. VGND $end
$var supply1 1 s. VPB $end
$var supply0 1 t. VNB $end

$scope module base $end
$var wire 1 C. Y $end
$var wire 1 _& A $end
$var wire 1 D. B $end
$var wire 1 u. nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 D. Y $end
$var wire 1 A. A $end
$var supply1 1 v. VPWR $end
$var supply0 1 w. VGND $end
$var supply1 1 x. VPB $end
$var supply0 1 y. VNB $end

$scope module base $end
$var wire 1 D. Y $end
$var wire 1 A. A $end
$var wire 1 z. not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 ?. Y $end
$var wire 1 A. A $end
$var wire 1 _& B $end
$var supply1 1 {. VPWR $end
$var supply0 1 |. VGND $end
$var supply1 1 }. VPB $end
$var supply0 1 ~. VNB $end

$scope module base $end
$var wire 1 ?. Y $end
$var wire 1 A. A $end
$var wire 1 _& B $end
$var wire 1 !/ nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_14__13 $end
$var wire 1 A. X $end
$var wire 1 `& A $end
$var supply1 1 "/ VPWR $end
$var supply0 1 #/ VGND $end
$var supply1 1 $/ VPB $end
$var supply0 1 %/ VNB $end

$scope module base $end
$var wire 1 A. X $end
$var wire 1 `& A $end
$var wire 1 &/ buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 i# in [0] $end
$var wire 1 3$ in [1] $end
$var wire 1 6$ in [2] $end
$var wire 1 9. mem [0] $end
$var wire 1 :. mem [1] $end
$var wire 1 ;. mem [2] $end
$var wire 1 <. mem_inv [0] $end
$var wire 1 =. mem_inv [1] $end
$var wire 1 >. mem_inv [2] $end
$var wire 1 E. out [0] $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 E. Z $end
$var wire 1 i# Q1 $end
$var wire 1 3$ Q2 $end
$var wire 1 6$ Q3 $end
$var wire 1 9. S0 $end
$var wire 1 <. S0B $end
$var wire 1 :. S1 $end
$var wire 1 =. S1B $end
$var wire 1 ;. S2 $end
$var wire 1 >. S2B $end
$var wire 1 '/ Q1__bar $end
$var wire 1 (/ Q2__bar $end
$var wire 1 )/ Q3__bar $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 E. in [0] $end
$var wire 1 9$ in [1] $end
$var wire 1 G. in [2] $end
$var wire 1 ?. mem [0] $end
$var wire 1 @. mem [1] $end
$var wire 1 A. mem [2] $end
$var wire 1 B. mem_inv [0] $end
$var wire 1 C. mem_inv [1] $end
$var wire 1 D. mem_inv [2] $end
$var wire 1 F. out [0] $end
$var wire 1 (' p0 $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 F. Z $end
$var wire 1 E. Q1 $end
$var wire 1 9$ Q2 $end
$var wire 1 (' Q3 $end
$var wire 1 ?. S0 $end
$var wire 1 B. S0B $end
$var wire 1 @. S1 $end
$var wire 1 C. S1B $end
$var wire 1 A. S2 $end
$var wire 1 D. S2B $end
$var wire 1 */ Q1__bar $end
$var wire 1 +/ Q2__bar $end
$var wire 1 ,/ Q3__bar $end
$upscope $end
$upscope $end

$scope module BINV_R_96 $end
$var wire 1 [$ Y $end
$var wire 1 H. A $end
$var supply1 1 -/ VPWR $end
$var supply0 1 ./ VGND $end
$var supply1 1 // VPB $end
$var supply0 1 0/ VNB $end

$scope module base $end
$var wire 1 [$ Y $end
$var wire 1 H. A $end
$var wire 1 1/ not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_97 $end
$var wire 1 H. Y $end
$var wire 1 F. A $end
$var supply1 1 2/ VPWR $end
$var supply0 1 3/ VGND $end
$var supply1 1 4/ VPB $end
$var supply0 1 5/ VNB $end

$scope module base $end
$var wire 1 H. Y $end
$var wire 1 F. A $end
$var wire 1 6/ not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_3 $end
$var wire 1 L# in [0] $end
$var wire 1 4$ in [1] $end
$var wire 1 7$ in [2] $end
$var wire 1 :$ in [3] $end
$var wire 1 a& sram [0] $end
$var wire 1 b& sram [1] $end
$var wire 1 c& sram [2] $end
$var wire 1 d& sram [3] $end
$var wire 1 :' sram_inv [0] $end
$var wire 1 ;' sram_inv [1] $end
$var wire 1 <' sram_inv [2] $end
$var wire 1 =' sram_inv [3] $end
$var wire 1 \$ out [0] $end
$var wire 1 (' p0 $end
$var wire 1 7/ local_encoder2to3_0_data [0] $end
$var wire 1 8/ local_encoder2to3_0_data [1] $end
$var wire 1 9/ local_encoder2to3_0_data [2] $end
$var wire 1 :/ local_encoder2to3_0_data_inv [0] $end
$var wire 1 ;/ local_encoder2to3_0_data_inv [1] $end
$var wire 1 </ local_encoder2to3_0_data_inv [2] $end
$var wire 1 =/ local_encoder2to3_1_data [0] $end
$var wire 1 >/ local_encoder2to3_1_data [1] $end
$var wire 1 ?/ local_encoder2to3_1_data [2] $end
$var wire 1 @/ local_encoder2to3_1_data_inv [0] $end
$var wire 1 A/ local_encoder2to3_1_data_inv [1] $end
$var wire 1 B/ local_encoder2to3_1_data_inv [2] $end
$var wire 1 C/ mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end
$var wire 1 D/ mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end
$var wire 1 E/ SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 F/ BUF_net_99 $end

$scope module local_encoder2to3_0_ $end
$var wire 1 a& addr [0] $end
$var wire 1 b& addr [1] $end
$var wire 1 7/ data [0] $end
$var wire 1 8/ data [1] $end
$var wire 1 9/ data [2] $end
$var wire 1 :/ data_inv [0] $end
$var wire 1 ;/ data_inv [1] $end
$var wire 1 </ data_inv [2] $end

$scope module U8 $end
$var wire 1 :/ Y $end
$var wire 1 7/ A $end
$var supply1 1 G/ VPWR $end
$var supply0 1 H/ VGND $end
$var supply1 1 I/ VPB $end
$var supply0 1 J/ VNB $end

$scope module base $end
$var wire 1 :/ Y $end
$var wire 1 7/ A $end
$var wire 1 K/ not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 8/ Y $end
$var wire 1 ;/ A $end
$var supply1 1 L/ VPWR $end
$var supply0 1 M/ VGND $end
$var supply1 1 N/ VPB $end
$var supply0 1 O/ VNB $end

$scope module base $end
$var wire 1 8/ Y $end
$var wire 1 ;/ A $end
$var wire 1 P/ not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 ;/ Y $end
$var wire 1 a& A $end
$var wire 1 </ B $end
$var supply1 1 Q/ VPWR $end
$var supply0 1 R/ VGND $end
$var supply1 1 S/ VPB $end
$var supply0 1 T/ VNB $end

$scope module base $end
$var wire 1 ;/ Y $end
$var wire 1 a& A $end
$var wire 1 </ B $end
$var wire 1 U/ nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 </ Y $end
$var wire 1 9/ A $end
$var supply1 1 V/ VPWR $end
$var supply0 1 W/ VGND $end
$var supply1 1 X/ VPB $end
$var supply0 1 Y/ VNB $end

$scope module base $end
$var wire 1 </ Y $end
$var wire 1 9/ A $end
$var wire 1 Z/ not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 7/ Y $end
$var wire 1 9/ A $end
$var wire 1 a& B $end
$var supply1 1 [/ VPWR $end
$var supply0 1 \/ VGND $end
$var supply1 1 ]/ VPB $end
$var supply0 1 ^/ VNB $end

$scope module base $end
$var wire 1 7/ Y $end
$var wire 1 9/ A $end
$var wire 1 a& B $end
$var wire 1 _/ nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_15__14 $end
$var wire 1 9/ X $end
$var wire 1 b& A $end
$var supply1 1 `/ VPWR $end
$var supply0 1 a/ VGND $end
$var supply1 1 b/ VPB $end
$var supply0 1 c/ VNB $end

$scope module base $end
$var wire 1 9/ X $end
$var wire 1 b& A $end
$var wire 1 d/ buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module local_encoder2to3_1_ $end
$var wire 1 c& addr [0] $end
$var wire 1 d& addr [1] $end
$var wire 1 =/ data [0] $end
$var wire 1 >/ data [1] $end
$var wire 1 ?/ data [2] $end
$var wire 1 @/ data_inv [0] $end
$var wire 1 A/ data_inv [1] $end
$var wire 1 B/ data_inv [2] $end

$scope module U8 $end
$var wire 1 @/ Y $end
$var wire 1 =/ A $end
$var supply1 1 e/ VPWR $end
$var supply0 1 f/ VGND $end
$var supply1 1 g/ VPB $end
$var supply0 1 h/ VNB $end

$scope module base $end
$var wire 1 @/ Y $end
$var wire 1 =/ A $end
$var wire 1 i/ not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 >/ Y $end
$var wire 1 A/ A $end
$var supply1 1 j/ VPWR $end
$var supply0 1 k/ VGND $end
$var supply1 1 l/ VPB $end
$var supply0 1 m/ VNB $end

$scope module base $end
$var wire 1 >/ Y $end
$var wire 1 A/ A $end
$var wire 1 n/ not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 A/ Y $end
$var wire 1 c& A $end
$var wire 1 B/ B $end
$var supply1 1 o/ VPWR $end
$var supply0 1 p/ VGND $end
$var supply1 1 q/ VPB $end
$var supply0 1 r/ VNB $end

$scope module base $end
$var wire 1 A/ Y $end
$var wire 1 c& A $end
$var wire 1 B/ B $end
$var wire 1 s/ nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 B/ Y $end
$var wire 1 ?/ A $end
$var supply1 1 t/ VPWR $end
$var supply0 1 u/ VGND $end
$var supply1 1 v/ VPB $end
$var supply0 1 w/ VNB $end

$scope module base $end
$var wire 1 B/ Y $end
$var wire 1 ?/ A $end
$var wire 1 x/ not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 =/ Y $end
$var wire 1 ?/ A $end
$var wire 1 c& B $end
$var supply1 1 y/ VPWR $end
$var supply0 1 z/ VGND $end
$var supply1 1 {/ VPB $end
$var supply0 1 |/ VNB $end

$scope module base $end
$var wire 1 =/ Y $end
$var wire 1 ?/ A $end
$var wire 1 c& B $end
$var wire 1 }/ nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_16__15 $end
$var wire 1 ?/ X $end
$var wire 1 d& A $end
$var supply1 1 ~/ VPWR $end
$var supply0 1 !0 VGND $end
$var supply1 1 "0 VPB $end
$var supply0 1 #0 VNB $end

$scope module base $end
$var wire 1 ?/ X $end
$var wire 1 d& A $end
$var wire 1 $0 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 L# in [0] $end
$var wire 1 4$ in [1] $end
$var wire 1 7$ in [2] $end
$var wire 1 7/ mem [0] $end
$var wire 1 8/ mem [1] $end
$var wire 1 9/ mem [2] $end
$var wire 1 :/ mem_inv [0] $end
$var wire 1 ;/ mem_inv [1] $end
$var wire 1 </ mem_inv [2] $end
$var wire 1 C/ out [0] $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 C/ Z $end
$var wire 1 L# Q1 $end
$var wire 1 4$ Q2 $end
$var wire 1 7$ Q3 $end
$var wire 1 7/ S0 $end
$var wire 1 :/ S0B $end
$var wire 1 8/ S1 $end
$var wire 1 ;/ S1B $end
$var wire 1 9/ S2 $end
$var wire 1 </ S2B $end
$var wire 1 %0 Q1__bar $end
$var wire 1 &0 Q2__bar $end
$var wire 1 '0 Q3__bar $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 C/ in [0] $end
$var wire 1 :$ in [1] $end
$var wire 1 E/ in [2] $end
$var wire 1 =/ mem [0] $end
$var wire 1 >/ mem [1] $end
$var wire 1 ?/ mem [2] $end
$var wire 1 @/ mem_inv [0] $end
$var wire 1 A/ mem_inv [1] $end
$var wire 1 B/ mem_inv [2] $end
$var wire 1 D/ out [0] $end
$var wire 1 (' p0 $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 D/ Z $end
$var wire 1 C/ Q1 $end
$var wire 1 :$ Q2 $end
$var wire 1 (' Q3 $end
$var wire 1 =/ S0 $end
$var wire 1 @/ S0B $end
$var wire 1 >/ S1 $end
$var wire 1 A/ S1B $end
$var wire 1 ?/ S2 $end
$var wire 1 B/ S2B $end
$var wire 1 (0 Q1__bar $end
$var wire 1 )0 Q2__bar $end
$var wire 1 *0 Q3__bar $end
$upscope $end
$upscope $end

$scope module BINV_R_98 $end
$var wire 1 \$ Y $end
$var wire 1 F/ A $end
$var supply1 1 +0 VPWR $end
$var supply0 1 ,0 VGND $end
$var supply1 1 -0 VPB $end
$var supply0 1 .0 VNB $end

$scope module base $end
$var wire 1 \$ Y $end
$var wire 1 F/ A $end
$var wire 1 /0 not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_99 $end
$var wire 1 F/ Y $end
$var wire 1 D/ A $end
$var supply1 1 00 VPWR $end
$var supply0 1 10 VGND $end
$var supply1 1 20 VPB $end
$var supply0 1 30 VNB $end

$scope module base $end
$var wire 1 F/ Y $end
$var wire 1 D/ A $end
$var wire 1 40 not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_5 $end
$var wire 1 M# in [0] $end
$var wire 1 5$ in [1] $end
$var wire 1 8$ in [2] $end
$var wire 1 ;$ in [3] $end
$var wire 1 e& sram [0] $end
$var wire 1 f& sram [1] $end
$var wire 1 g& sram [2] $end
$var wire 1 h& sram [3] $end
$var wire 1 >' sram_inv [0] $end
$var wire 1 ?' sram_inv [1] $end
$var wire 1 @' sram_inv [2] $end
$var wire 1 A' sram_inv [3] $end
$var wire 1 ]$ out [0] $end
$var wire 1 (' p0 $end
$var wire 1 50 local_encoder2to3_0_data [0] $end
$var wire 1 60 local_encoder2to3_0_data [1] $end
$var wire 1 70 local_encoder2to3_0_data [2] $end
$var wire 1 80 local_encoder2to3_0_data_inv [0] $end
$var wire 1 90 local_encoder2to3_0_data_inv [1] $end
$var wire 1 :0 local_encoder2to3_0_data_inv [2] $end
$var wire 1 ;0 local_encoder2to3_1_data [0] $end
$var wire 1 <0 local_encoder2to3_1_data [1] $end
$var wire 1 =0 local_encoder2to3_1_data [2] $end
$var wire 1 >0 local_encoder2to3_1_data_inv [0] $end
$var wire 1 ?0 local_encoder2to3_1_data_inv [1] $end
$var wire 1 @0 local_encoder2to3_1_data_inv [2] $end
$var wire 1 A0 mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end
$var wire 1 B0 mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end
$var wire 1 C0 SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 D0 BUF_net_101 $end

$scope module local_encoder2to3_0_ $end
$var wire 1 e& addr [0] $end
$var wire 1 f& addr [1] $end
$var wire 1 50 data [0] $end
$var wire 1 60 data [1] $end
$var wire 1 70 data [2] $end
$var wire 1 80 data_inv [0] $end
$var wire 1 90 data_inv [1] $end
$var wire 1 :0 data_inv [2] $end

$scope module U8 $end
$var wire 1 80 Y $end
$var wire 1 50 A $end
$var supply1 1 E0 VPWR $end
$var supply0 1 F0 VGND $end
$var supply1 1 G0 VPB $end
$var supply0 1 H0 VNB $end

$scope module base $end
$var wire 1 80 Y $end
$var wire 1 50 A $end
$var wire 1 I0 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 60 Y $end
$var wire 1 90 A $end
$var supply1 1 J0 VPWR $end
$var supply0 1 K0 VGND $end
$var supply1 1 L0 VPB $end
$var supply0 1 M0 VNB $end

$scope module base $end
$var wire 1 60 Y $end
$var wire 1 90 A $end
$var wire 1 N0 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 90 Y $end
$var wire 1 e& A $end
$var wire 1 :0 B $end
$var supply1 1 O0 VPWR $end
$var supply0 1 P0 VGND $end
$var supply1 1 Q0 VPB $end
$var supply0 1 R0 VNB $end

$scope module base $end
$var wire 1 90 Y $end
$var wire 1 e& A $end
$var wire 1 :0 B $end
$var wire 1 S0 nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 :0 Y $end
$var wire 1 70 A $end
$var supply1 1 T0 VPWR $end
$var supply0 1 U0 VGND $end
$var supply1 1 V0 VPB $end
$var supply0 1 W0 VNB $end

$scope module base $end
$var wire 1 :0 Y $end
$var wire 1 70 A $end
$var wire 1 X0 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 50 Y $end
$var wire 1 70 A $end
$var wire 1 e& B $end
$var supply1 1 Y0 VPWR $end
$var supply0 1 Z0 VGND $end
$var supply1 1 [0 VPB $end
$var supply0 1 \0 VNB $end

$scope module base $end
$var wire 1 50 Y $end
$var wire 1 70 A $end
$var wire 1 e& B $end
$var wire 1 ]0 nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_17__16 $end
$var wire 1 70 X $end
$var wire 1 f& A $end
$var supply1 1 ^0 VPWR $end
$var supply0 1 _0 VGND $end
$var supply1 1 `0 VPB $end
$var supply0 1 a0 VNB $end

$scope module base $end
$var wire 1 70 X $end
$var wire 1 f& A $end
$var wire 1 b0 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module local_encoder2to3_1_ $end
$var wire 1 g& addr [0] $end
$var wire 1 h& addr [1] $end
$var wire 1 ;0 data [0] $end
$var wire 1 <0 data [1] $end
$var wire 1 =0 data [2] $end
$var wire 1 >0 data_inv [0] $end
$var wire 1 ?0 data_inv [1] $end
$var wire 1 @0 data_inv [2] $end

$scope module U8 $end
$var wire 1 >0 Y $end
$var wire 1 ;0 A $end
$var supply1 1 c0 VPWR $end
$var supply0 1 d0 VGND $end
$var supply1 1 e0 VPB $end
$var supply0 1 f0 VNB $end

$scope module base $end
$var wire 1 >0 Y $end
$var wire 1 ;0 A $end
$var wire 1 g0 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 <0 Y $end
$var wire 1 ?0 A $end
$var supply1 1 h0 VPWR $end
$var supply0 1 i0 VGND $end
$var supply1 1 j0 VPB $end
$var supply0 1 k0 VNB $end

$scope module base $end
$var wire 1 <0 Y $end
$var wire 1 ?0 A $end
$var wire 1 l0 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 ?0 Y $end
$var wire 1 g& A $end
$var wire 1 @0 B $end
$var supply1 1 m0 VPWR $end
$var supply0 1 n0 VGND $end
$var supply1 1 o0 VPB $end
$var supply0 1 p0 VNB $end

$scope module base $end
$var wire 1 ?0 Y $end
$var wire 1 g& A $end
$var wire 1 @0 B $end
$var wire 1 q0 nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 @0 Y $end
$var wire 1 =0 A $end
$var supply1 1 r0 VPWR $end
$var supply0 1 s0 VGND $end
$var supply1 1 t0 VPB $end
$var supply0 1 u0 VNB $end

$scope module base $end
$var wire 1 @0 Y $end
$var wire 1 =0 A $end
$var wire 1 v0 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 ;0 Y $end
$var wire 1 =0 A $end
$var wire 1 g& B $end
$var supply1 1 w0 VPWR $end
$var supply0 1 x0 VGND $end
$var supply1 1 y0 VPB $end
$var supply0 1 z0 VNB $end

$scope module base $end
$var wire 1 ;0 Y $end
$var wire 1 =0 A $end
$var wire 1 g& B $end
$var wire 1 {0 nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_18__17 $end
$var wire 1 =0 X $end
$var wire 1 h& A $end
$var supply1 1 |0 VPWR $end
$var supply0 1 }0 VGND $end
$var supply1 1 ~0 VPB $end
$var supply0 1 !1 VNB $end

$scope module base $end
$var wire 1 =0 X $end
$var wire 1 h& A $end
$var wire 1 "1 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 M# in [0] $end
$var wire 1 5$ in [1] $end
$var wire 1 8$ in [2] $end
$var wire 1 50 mem [0] $end
$var wire 1 60 mem [1] $end
$var wire 1 70 mem [2] $end
$var wire 1 80 mem_inv [0] $end
$var wire 1 90 mem_inv [1] $end
$var wire 1 :0 mem_inv [2] $end
$var wire 1 A0 out [0] $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 A0 Z $end
$var wire 1 M# Q1 $end
$var wire 1 5$ Q2 $end
$var wire 1 8$ Q3 $end
$var wire 1 50 S0 $end
$var wire 1 80 S0B $end
$var wire 1 60 S1 $end
$var wire 1 90 S1B $end
$var wire 1 70 S2 $end
$var wire 1 :0 S2B $end
$var wire 1 #1 Q1__bar $end
$var wire 1 $1 Q2__bar $end
$var wire 1 %1 Q3__bar $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 A0 in [0] $end
$var wire 1 ;$ in [1] $end
$var wire 1 C0 in [2] $end
$var wire 1 ;0 mem [0] $end
$var wire 1 <0 mem [1] $end
$var wire 1 =0 mem [2] $end
$var wire 1 >0 mem_inv [0] $end
$var wire 1 ?0 mem_inv [1] $end
$var wire 1 @0 mem_inv [2] $end
$var wire 1 B0 out [0] $end
$var wire 1 (' p0 $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 B0 Z $end
$var wire 1 A0 Q1 $end
$var wire 1 ;$ Q2 $end
$var wire 1 (' Q3 $end
$var wire 1 ;0 S0 $end
$var wire 1 >0 S0B $end
$var wire 1 <0 S1 $end
$var wire 1 ?0 S1B $end
$var wire 1 =0 S2 $end
$var wire 1 @0 S2B $end
$var wire 1 &1 Q1__bar $end
$var wire 1 '1 Q2__bar $end
$var wire 1 (1 Q3__bar $end
$upscope $end
$upscope $end

$scope module BINV_R_100 $end
$var wire 1 ]$ Y $end
$var wire 1 D0 A $end
$var supply1 1 )1 VPWR $end
$var supply0 1 *1 VGND $end
$var supply1 1 +1 VPB $end
$var supply0 1 ,1 VNB $end

$scope module base $end
$var wire 1 ]$ Y $end
$var wire 1 D0 A $end
$var wire 1 -1 not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_101 $end
$var wire 1 D0 Y $end
$var wire 1 B0 A $end
$var supply1 1 .1 VPWR $end
$var supply0 1 /1 VGND $end
$var supply1 1 01 VPB $end
$var supply0 1 11 VNB $end

$scope module base $end
$var wire 1 D0 Y $end
$var wire 1 B0 A $end
$var wire 1 21 not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_7 $end
$var wire 1 N# in [0] $end
$var wire 1 3$ in [1] $end
$var wire 1 6$ in [2] $end
$var wire 1 9$ in [3] $end
$var wire 1 i& sram [0] $end
$var wire 1 j& sram [1] $end
$var wire 1 k& sram [2] $end
$var wire 1 l& sram [3] $end
$var wire 1 B' sram_inv [0] $end
$var wire 1 C' sram_inv [1] $end
$var wire 1 D' sram_inv [2] $end
$var wire 1 E' sram_inv [3] $end
$var wire 1 ^$ out [0] $end
$var wire 1 (' p0 $end
$var wire 1 31 local_encoder2to3_0_data [0] $end
$var wire 1 41 local_encoder2to3_0_data [1] $end
$var wire 1 51 local_encoder2to3_0_data [2] $end
$var wire 1 61 local_encoder2to3_0_data_inv [0] $end
$var wire 1 71 local_encoder2to3_0_data_inv [1] $end
$var wire 1 81 local_encoder2to3_0_data_inv [2] $end
$var wire 1 91 local_encoder2to3_1_data [0] $end
$var wire 1 :1 local_encoder2to3_1_data [1] $end
$var wire 1 ;1 local_encoder2to3_1_data [2] $end
$var wire 1 <1 local_encoder2to3_1_data_inv [0] $end
$var wire 1 =1 local_encoder2to3_1_data_inv [1] $end
$var wire 1 >1 local_encoder2to3_1_data_inv [2] $end
$var wire 1 ?1 mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end
$var wire 1 @1 mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end
$var wire 1 A1 SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 B1 BUF_net_103 $end

$scope module local_encoder2to3_0_ $end
$var wire 1 i& addr [0] $end
$var wire 1 j& addr [1] $end
$var wire 1 31 data [0] $end
$var wire 1 41 data [1] $end
$var wire 1 51 data [2] $end
$var wire 1 61 data_inv [0] $end
$var wire 1 71 data_inv [1] $end
$var wire 1 81 data_inv [2] $end

$scope module U8 $end
$var wire 1 61 Y $end
$var wire 1 31 A $end
$var supply1 1 C1 VPWR $end
$var supply0 1 D1 VGND $end
$var supply1 1 E1 VPB $end
$var supply0 1 F1 VNB $end

$scope module base $end
$var wire 1 61 Y $end
$var wire 1 31 A $end
$var wire 1 G1 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 41 Y $end
$var wire 1 71 A $end
$var supply1 1 H1 VPWR $end
$var supply0 1 I1 VGND $end
$var supply1 1 J1 VPB $end
$var supply0 1 K1 VNB $end

$scope module base $end
$var wire 1 41 Y $end
$var wire 1 71 A $end
$var wire 1 L1 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 71 Y $end
$var wire 1 i& A $end
$var wire 1 81 B $end
$var supply1 1 M1 VPWR $end
$var supply0 1 N1 VGND $end
$var supply1 1 O1 VPB $end
$var supply0 1 P1 VNB $end

$scope module base $end
$var wire 1 71 Y $end
$var wire 1 i& A $end
$var wire 1 81 B $end
$var wire 1 Q1 nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 81 Y $end
$var wire 1 51 A $end
$var supply1 1 R1 VPWR $end
$var supply0 1 S1 VGND $end
$var supply1 1 T1 VPB $end
$var supply0 1 U1 VNB $end

$scope module base $end
$var wire 1 81 Y $end
$var wire 1 51 A $end
$var wire 1 V1 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 31 Y $end
$var wire 1 51 A $end
$var wire 1 i& B $end
$var supply1 1 W1 VPWR $end
$var supply0 1 X1 VGND $end
$var supply1 1 Y1 VPB $end
$var supply0 1 Z1 VNB $end

$scope module base $end
$var wire 1 31 Y $end
$var wire 1 51 A $end
$var wire 1 i& B $end
$var wire 1 [1 nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_19__18 $end
$var wire 1 51 X $end
$var wire 1 j& A $end
$var supply1 1 \1 VPWR $end
$var supply0 1 ]1 VGND $end
$var supply1 1 ^1 VPB $end
$var supply0 1 _1 VNB $end

$scope module base $end
$var wire 1 51 X $end
$var wire 1 j& A $end
$var wire 1 `1 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module local_encoder2to3_1_ $end
$var wire 1 k& addr [0] $end
$var wire 1 l& addr [1] $end
$var wire 1 91 data [0] $end
$var wire 1 :1 data [1] $end
$var wire 1 ;1 data [2] $end
$var wire 1 <1 data_inv [0] $end
$var wire 1 =1 data_inv [1] $end
$var wire 1 >1 data_inv [2] $end

$scope module U8 $end
$var wire 1 <1 Y $end
$var wire 1 91 A $end
$var supply1 1 a1 VPWR $end
$var supply0 1 b1 VGND $end
$var supply1 1 c1 VPB $end
$var supply0 1 d1 VNB $end

$scope module base $end
$var wire 1 <1 Y $end
$var wire 1 91 A $end
$var wire 1 e1 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 :1 Y $end
$var wire 1 =1 A $end
$var supply1 1 f1 VPWR $end
$var supply0 1 g1 VGND $end
$var supply1 1 h1 VPB $end
$var supply0 1 i1 VNB $end

$scope module base $end
$var wire 1 :1 Y $end
$var wire 1 =1 A $end
$var wire 1 j1 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 =1 Y $end
$var wire 1 k& A $end
$var wire 1 >1 B $end
$var supply1 1 k1 VPWR $end
$var supply0 1 l1 VGND $end
$var supply1 1 m1 VPB $end
$var supply0 1 n1 VNB $end

$scope module base $end
$var wire 1 =1 Y $end
$var wire 1 k& A $end
$var wire 1 >1 B $end
$var wire 1 o1 nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 >1 Y $end
$var wire 1 ;1 A $end
$var supply1 1 p1 VPWR $end
$var supply0 1 q1 VGND $end
$var supply1 1 r1 VPB $end
$var supply0 1 s1 VNB $end

$scope module base $end
$var wire 1 >1 Y $end
$var wire 1 ;1 A $end
$var wire 1 t1 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 91 Y $end
$var wire 1 ;1 A $end
$var wire 1 k& B $end
$var supply1 1 u1 VPWR $end
$var supply0 1 v1 VGND $end
$var supply1 1 w1 VPB $end
$var supply0 1 x1 VNB $end

$scope module base $end
$var wire 1 91 Y $end
$var wire 1 ;1 A $end
$var wire 1 k& B $end
$var wire 1 y1 nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_20__19 $end
$var wire 1 ;1 X $end
$var wire 1 l& A $end
$var supply1 1 z1 VPWR $end
$var supply0 1 {1 VGND $end
$var supply1 1 |1 VPB $end
$var supply0 1 }1 VNB $end

$scope module base $end
$var wire 1 ;1 X $end
$var wire 1 l& A $end
$var wire 1 ~1 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 N# in [0] $end
$var wire 1 3$ in [1] $end
$var wire 1 6$ in [2] $end
$var wire 1 31 mem [0] $end
$var wire 1 41 mem [1] $end
$var wire 1 51 mem [2] $end
$var wire 1 61 mem_inv [0] $end
$var wire 1 71 mem_inv [1] $end
$var wire 1 81 mem_inv [2] $end
$var wire 1 ?1 out [0] $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 ?1 Z $end
$var wire 1 N# Q1 $end
$var wire 1 3$ Q2 $end
$var wire 1 6$ Q3 $end
$var wire 1 31 S0 $end
$var wire 1 61 S0B $end
$var wire 1 41 S1 $end
$var wire 1 71 S1B $end
$var wire 1 51 S2 $end
$var wire 1 81 S2B $end
$var wire 1 !2 Q1__bar $end
$var wire 1 "2 Q2__bar $end
$var wire 1 #2 Q3__bar $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 ?1 in [0] $end
$var wire 1 9$ in [1] $end
$var wire 1 A1 in [2] $end
$var wire 1 91 mem [0] $end
$var wire 1 :1 mem [1] $end
$var wire 1 ;1 mem [2] $end
$var wire 1 <1 mem_inv [0] $end
$var wire 1 =1 mem_inv [1] $end
$var wire 1 >1 mem_inv [2] $end
$var wire 1 @1 out [0] $end
$var wire 1 (' p0 $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 @1 Z $end
$var wire 1 ?1 Q1 $end
$var wire 1 9$ Q2 $end
$var wire 1 (' Q3 $end
$var wire 1 91 S0 $end
$var wire 1 <1 S0B $end
$var wire 1 :1 S1 $end
$var wire 1 =1 S1B $end
$var wire 1 ;1 S2 $end
$var wire 1 >1 S2B $end
$var wire 1 $2 Q1__bar $end
$var wire 1 %2 Q2__bar $end
$var wire 1 &2 Q3__bar $end
$upscope $end
$upscope $end

$scope module BINV_R_102 $end
$var wire 1 ^$ Y $end
$var wire 1 B1 A $end
$var supply1 1 '2 VPWR $end
$var supply0 1 (2 VGND $end
$var supply1 1 )2 VPB $end
$var supply0 1 *2 VNB $end

$scope module base $end
$var wire 1 ^$ Y $end
$var wire 1 B1 A $end
$var wire 1 +2 not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_103 $end
$var wire 1 B1 Y $end
$var wire 1 @1 A $end
$var supply1 1 ,2 VPWR $end
$var supply0 1 -2 VGND $end
$var supply1 1 .2 VPB $end
$var supply0 1 /2 VNB $end

$scope module base $end
$var wire 1 B1 Y $end
$var wire 1 @1 A $end
$var wire 1 02 not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_9 $end
$var wire 1 O# in [0] $end
$var wire 1 4$ in [1] $end
$var wire 1 7$ in [2] $end
$var wire 1 :$ in [3] $end
$var wire 1 A& sram [0] $end
$var wire 1 B& sram [1] $end
$var wire 1 C& sram [2] $end
$var wire 1 D& sram [3] $end
$var wire 1 F' sram_inv [0] $end
$var wire 1 G' sram_inv [1] $end
$var wire 1 H' sram_inv [2] $end
$var wire 1 I' sram_inv [3] $end
$var wire 1 _$ out [0] $end
$var wire 1 (' p0 $end
$var wire 1 12 local_encoder2to3_0_data [0] $end
$var wire 1 22 local_encoder2to3_0_data [1] $end
$var wire 1 32 local_encoder2to3_0_data [2] $end
$var wire 1 42 local_encoder2to3_0_data_inv [0] $end
$var wire 1 52 local_encoder2to3_0_data_inv [1] $end
$var wire 1 62 local_encoder2to3_0_data_inv [2] $end
$var wire 1 72 local_encoder2to3_1_data [0] $end
$var wire 1 82 local_encoder2to3_1_data [1] $end
$var wire 1 92 local_encoder2to3_1_data [2] $end
$var wire 1 :2 local_encoder2to3_1_data_inv [0] $end
$var wire 1 ;2 local_encoder2to3_1_data_inv [1] $end
$var wire 1 <2 local_encoder2to3_1_data_inv [2] $end
$var wire 1 =2 mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end
$var wire 1 >2 mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end
$var wire 1 ?2 SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 @2 BUF_net_105 $end

$scope module local_encoder2to3_0_ $end
$var wire 1 A& addr [0] $end
$var wire 1 B& addr [1] $end
$var wire 1 12 data [0] $end
$var wire 1 22 data [1] $end
$var wire 1 32 data [2] $end
$var wire 1 42 data_inv [0] $end
$var wire 1 52 data_inv [1] $end
$var wire 1 62 data_inv [2] $end

$scope module U8 $end
$var wire 1 42 Y $end
$var wire 1 12 A $end
$var supply1 1 A2 VPWR $end
$var supply0 1 B2 VGND $end
$var supply1 1 C2 VPB $end
$var supply0 1 D2 VNB $end

$scope module base $end
$var wire 1 42 Y $end
$var wire 1 12 A $end
$var wire 1 E2 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 22 Y $end
$var wire 1 52 A $end
$var supply1 1 F2 VPWR $end
$var supply0 1 G2 VGND $end
$var supply1 1 H2 VPB $end
$var supply0 1 I2 VNB $end

$scope module base $end
$var wire 1 22 Y $end
$var wire 1 52 A $end
$var wire 1 J2 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 52 Y $end
$var wire 1 A& A $end
$var wire 1 62 B $end
$var supply1 1 K2 VPWR $end
$var supply0 1 L2 VGND $end
$var supply1 1 M2 VPB $end
$var supply0 1 N2 VNB $end

$scope module base $end
$var wire 1 52 Y $end
$var wire 1 A& A $end
$var wire 1 62 B $end
$var wire 1 O2 nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 62 Y $end
$var wire 1 32 A $end
$var supply1 1 P2 VPWR $end
$var supply0 1 Q2 VGND $end
$var supply1 1 R2 VPB $end
$var supply0 1 S2 VNB $end

$scope module base $end
$var wire 1 62 Y $end
$var wire 1 32 A $end
$var wire 1 T2 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 12 Y $end
$var wire 1 32 A $end
$var wire 1 A& B $end
$var supply1 1 U2 VPWR $end
$var supply0 1 V2 VGND $end
$var supply1 1 W2 VPB $end
$var supply0 1 X2 VNB $end

$scope module base $end
$var wire 1 12 Y $end
$var wire 1 32 A $end
$var wire 1 A& B $end
$var wire 1 Y2 nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_21__20 $end
$var wire 1 32 X $end
$var wire 1 B& A $end
$var supply1 1 Z2 VPWR $end
$var supply0 1 [2 VGND $end
$var supply1 1 \2 VPB $end
$var supply0 1 ]2 VNB $end

$scope module base $end
$var wire 1 32 X $end
$var wire 1 B& A $end
$var wire 1 ^2 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module local_encoder2to3_1_ $end
$var wire 1 C& addr [0] $end
$var wire 1 D& addr [1] $end
$var wire 1 72 data [0] $end
$var wire 1 82 data [1] $end
$var wire 1 92 data [2] $end
$var wire 1 :2 data_inv [0] $end
$var wire 1 ;2 data_inv [1] $end
$var wire 1 <2 data_inv [2] $end

$scope module U8 $end
$var wire 1 :2 Y $end
$var wire 1 72 A $end
$var supply1 1 _2 VPWR $end
$var supply0 1 `2 VGND $end
$var supply1 1 a2 VPB $end
$var supply0 1 b2 VNB $end

$scope module base $end
$var wire 1 :2 Y $end
$var wire 1 72 A $end
$var wire 1 c2 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 82 Y $end
$var wire 1 ;2 A $end
$var supply1 1 d2 VPWR $end
$var supply0 1 e2 VGND $end
$var supply1 1 f2 VPB $end
$var supply0 1 g2 VNB $end

$scope module base $end
$var wire 1 82 Y $end
$var wire 1 ;2 A $end
$var wire 1 h2 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 ;2 Y $end
$var wire 1 C& A $end
$var wire 1 <2 B $end
$var supply1 1 i2 VPWR $end
$var supply0 1 j2 VGND $end
$var supply1 1 k2 VPB $end
$var supply0 1 l2 VNB $end

$scope module base $end
$var wire 1 ;2 Y $end
$var wire 1 C& A $end
$var wire 1 <2 B $end
$var wire 1 m2 nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 <2 Y $end
$var wire 1 92 A $end
$var supply1 1 n2 VPWR $end
$var supply0 1 o2 VGND $end
$var supply1 1 p2 VPB $end
$var supply0 1 q2 VNB $end

$scope module base $end
$var wire 1 <2 Y $end
$var wire 1 92 A $end
$var wire 1 r2 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 72 Y $end
$var wire 1 92 A $end
$var wire 1 C& B $end
$var supply1 1 s2 VPWR $end
$var supply0 1 t2 VGND $end
$var supply1 1 u2 VPB $end
$var supply0 1 v2 VNB $end

$scope module base $end
$var wire 1 72 Y $end
$var wire 1 92 A $end
$var wire 1 C& B $end
$var wire 1 w2 nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_22__21 $end
$var wire 1 92 X $end
$var wire 1 D& A $end
$var supply1 1 x2 VPWR $end
$var supply0 1 y2 VGND $end
$var supply1 1 z2 VPB $end
$var supply0 1 {2 VNB $end

$scope module base $end
$var wire 1 92 X $end
$var wire 1 D& A $end
$var wire 1 |2 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 O# in [0] $end
$var wire 1 4$ in [1] $end
$var wire 1 7$ in [2] $end
$var wire 1 12 mem [0] $end
$var wire 1 22 mem [1] $end
$var wire 1 32 mem [2] $end
$var wire 1 42 mem_inv [0] $end
$var wire 1 52 mem_inv [1] $end
$var wire 1 62 mem_inv [2] $end
$var wire 1 =2 out [0] $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 =2 Z $end
$var wire 1 O# Q1 $end
$var wire 1 4$ Q2 $end
$var wire 1 7$ Q3 $end
$var wire 1 12 S0 $end
$var wire 1 42 S0B $end
$var wire 1 22 S1 $end
$var wire 1 52 S1B $end
$var wire 1 32 S2 $end
$var wire 1 62 S2B $end
$var wire 1 }2 Q1__bar $end
$var wire 1 ~2 Q2__bar $end
$var wire 1 !3 Q3__bar $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 =2 in [0] $end
$var wire 1 :$ in [1] $end
$var wire 1 ?2 in [2] $end
$var wire 1 72 mem [0] $end
$var wire 1 82 mem [1] $end
$var wire 1 92 mem [2] $end
$var wire 1 :2 mem_inv [0] $end
$var wire 1 ;2 mem_inv [1] $end
$var wire 1 <2 mem_inv [2] $end
$var wire 1 >2 out [0] $end
$var wire 1 (' p0 $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 >2 Z $end
$var wire 1 =2 Q1 $end
$var wire 1 :$ Q2 $end
$var wire 1 (' Q3 $end
$var wire 1 72 S0 $end
$var wire 1 :2 S0B $end
$var wire 1 82 S1 $end
$var wire 1 ;2 S1B $end
$var wire 1 92 S2 $end
$var wire 1 <2 S2B $end
$var wire 1 "3 Q1__bar $end
$var wire 1 #3 Q2__bar $end
$var wire 1 $3 Q3__bar $end
$upscope $end
$upscope $end

$scope module BINV_R_104 $end
$var wire 1 _$ Y $end
$var wire 1 @2 A $end
$var supply1 1 %3 VPWR $end
$var supply0 1 &3 VGND $end
$var supply1 1 '3 VPB $end
$var supply0 1 (3 VNB $end

$scope module base $end
$var wire 1 _$ Y $end
$var wire 1 @2 A $end
$var wire 1 )3 not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_105 $end
$var wire 1 @2 Y $end
$var wire 1 >2 A $end
$var supply1 1 *3 VPWR $end
$var supply0 1 +3 VGND $end
$var supply1 1 ,3 VPB $end
$var supply0 1 -3 VNB $end

$scope module base $end
$var wire 1 @2 Y $end
$var wire 1 >2 A $end
$var wire 1 .3 not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_11 $end
$var wire 1 P# in [0] $end
$var wire 1 5$ in [1] $end
$var wire 1 8$ in [2] $end
$var wire 1 ;$ in [3] $end
$var wire 1 E& sram [0] $end
$var wire 1 F& sram [1] $end
$var wire 1 G& sram [2] $end
$var wire 1 H& sram [3] $end
$var wire 1 J' sram_inv [0] $end
$var wire 1 K' sram_inv [1] $end
$var wire 1 L' sram_inv [2] $end
$var wire 1 M' sram_inv [3] $end
$var wire 1 `$ out [0] $end
$var wire 1 (' p0 $end
$var wire 1 /3 local_encoder2to3_0_data [0] $end
$var wire 1 03 local_encoder2to3_0_data [1] $end
$var wire 1 13 local_encoder2to3_0_data [2] $end
$var wire 1 23 local_encoder2to3_0_data_inv [0] $end
$var wire 1 33 local_encoder2to3_0_data_inv [1] $end
$var wire 1 43 local_encoder2to3_0_data_inv [2] $end
$var wire 1 53 local_encoder2to3_1_data [0] $end
$var wire 1 63 local_encoder2to3_1_data [1] $end
$var wire 1 73 local_encoder2to3_1_data [2] $end
$var wire 1 83 local_encoder2to3_1_data_inv [0] $end
$var wire 1 93 local_encoder2to3_1_data_inv [1] $end
$var wire 1 :3 local_encoder2to3_1_data_inv [2] $end
$var wire 1 ;3 mux_2level_tapbuf_basis_input3_mem3_0_out [0] $end
$var wire 1 <3 mux_2level_tapbuf_basis_input3_mem3_1_out [0] $end
$var wire 1 =3 SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 >3 BUF_net_107 $end

$scope module local_encoder2to3_0_ $end
$var wire 1 E& addr [0] $end
$var wire 1 F& addr [1] $end
$var wire 1 /3 data [0] $end
$var wire 1 03 data [1] $end
$var wire 1 13 data [2] $end
$var wire 1 23 data_inv [0] $end
$var wire 1 33 data_inv [1] $end
$var wire 1 43 data_inv [2] $end

$scope module U8 $end
$var wire 1 23 Y $end
$var wire 1 /3 A $end
$var supply1 1 ?3 VPWR $end
$var supply0 1 @3 VGND $end
$var supply1 1 A3 VPB $end
$var supply0 1 B3 VNB $end

$scope module base $end
$var wire 1 23 Y $end
$var wire 1 /3 A $end
$var wire 1 C3 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 03 Y $end
$var wire 1 33 A $end
$var supply1 1 D3 VPWR $end
$var supply0 1 E3 VGND $end
$var supply1 1 F3 VPB $end
$var supply0 1 G3 VNB $end

$scope module base $end
$var wire 1 03 Y $end
$var wire 1 33 A $end
$var wire 1 H3 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 33 Y $end
$var wire 1 E& A $end
$var wire 1 43 B $end
$var supply1 1 I3 VPWR $end
$var supply0 1 J3 VGND $end
$var supply1 1 K3 VPB $end
$var supply0 1 L3 VNB $end

$scope module base $end
$var wire 1 33 Y $end
$var wire 1 E& A $end
$var wire 1 43 B $end
$var wire 1 M3 nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 43 Y $end
$var wire 1 13 A $end
$var supply1 1 N3 VPWR $end
$var supply0 1 O3 VGND $end
$var supply1 1 P3 VPB $end
$var supply0 1 Q3 VNB $end

$scope module base $end
$var wire 1 43 Y $end
$var wire 1 13 A $end
$var wire 1 R3 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 /3 Y $end
$var wire 1 13 A $end
$var wire 1 E& B $end
$var supply1 1 S3 VPWR $end
$var supply0 1 T3 VGND $end
$var supply1 1 U3 VPB $end
$var supply0 1 V3 VNB $end

$scope module base $end
$var wire 1 /3 Y $end
$var wire 1 13 A $end
$var wire 1 E& B $end
$var wire 1 W3 nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_23__22 $end
$var wire 1 13 X $end
$var wire 1 F& A $end
$var supply1 1 X3 VPWR $end
$var supply0 1 Y3 VGND $end
$var supply1 1 Z3 VPB $end
$var supply0 1 [3 VNB $end

$scope module base $end
$var wire 1 13 X $end
$var wire 1 F& A $end
$var wire 1 \3 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module local_encoder2to3_1_ $end
$var wire 1 G& addr [0] $end
$var wire 1 H& addr [1] $end
$var wire 1 53 data [0] $end
$var wire 1 63 data [1] $end
$var wire 1 73 data [2] $end
$var wire 1 83 data_inv [0] $end
$var wire 1 93 data_inv [1] $end
$var wire 1 :3 data_inv [2] $end

$scope module U8 $end
$var wire 1 83 Y $end
$var wire 1 53 A $end
$var supply1 1 ]3 VPWR $end
$var supply0 1 ^3 VGND $end
$var supply1 1 _3 VPB $end
$var supply0 1 `3 VNB $end

$scope module base $end
$var wire 1 83 Y $end
$var wire 1 53 A $end
$var wire 1 a3 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U9 $end
$var wire 1 63 Y $end
$var wire 1 93 A $end
$var supply1 1 b3 VPWR $end
$var supply0 1 c3 VGND $end
$var supply1 1 d3 VPB $end
$var supply0 1 e3 VNB $end

$scope module base $end
$var wire 1 63 Y $end
$var wire 1 93 A $end
$var wire 1 f3 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U10 $end
$var wire 1 93 Y $end
$var wire 1 G& A $end
$var wire 1 :3 B $end
$var supply1 1 g3 VPWR $end
$var supply0 1 h3 VGND $end
$var supply1 1 i3 VPB $end
$var supply0 1 j3 VNB $end

$scope module base $end
$var wire 1 93 Y $end
$var wire 1 G& A $end
$var wire 1 :3 B $end
$var wire 1 k3 nand0_out_Y $end
$upscope $end
$upscope $end

$scope module U11 $end
$var wire 1 :3 Y $end
$var wire 1 73 A $end
$var supply1 1 l3 VPWR $end
$var supply0 1 m3 VGND $end
$var supply1 1 n3 VPB $end
$var supply0 1 o3 VNB $end

$scope module base $end
$var wire 1 :3 Y $end
$var wire 1 73 A $end
$var wire 1 p3 not0_out_Y $end
$upscope $end
$upscope $end

$scope module U12 $end
$var wire 1 53 Y $end
$var wire 1 73 A $end
$var wire 1 G& B $end
$var supply1 1 q3 VPWR $end
$var supply0 1 r3 VGND $end
$var supply1 1 s3 VPB $end
$var supply0 1 t3 VNB $end

$scope module base $end
$var wire 1 53 Y $end
$var wire 1 73 A $end
$var wire 1 G& B $end
$var wire 1 u3 nor0_out_Y $end
$upscope $end
$upscope $end

$scope module FTB_24__23 $end
$var wire 1 73 X $end
$var wire 1 H& A $end
$var supply1 1 v3 VPWR $end
$var supply0 1 w3 VGND $end
$var supply1 1 x3 VPB $end
$var supply0 1 y3 VNB $end

$scope module base $end
$var wire 1 73 X $end
$var wire 1 H& A $end
$var wire 1 z3 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 P# in [0] $end
$var wire 1 5$ in [1] $end
$var wire 1 8$ in [2] $end
$var wire 1 /3 mem [0] $end
$var wire 1 03 mem [1] $end
$var wire 1 13 mem [2] $end
$var wire 1 23 mem_inv [0] $end
$var wire 1 33 mem_inv [1] $end
$var wire 1 43 mem_inv [2] $end
$var wire 1 ;3 out [0] $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 ;3 Z $end
$var wire 1 P# Q1 $end
$var wire 1 5$ Q2 $end
$var wire 1 8$ Q3 $end
$var wire 1 /3 S0 $end
$var wire 1 23 S0B $end
$var wire 1 03 S1 $end
$var wire 1 33 S1B $end
$var wire 1 13 S2 $end
$var wire 1 43 S2B $end
$var wire 1 {3 Q1__bar $end
$var wire 1 |3 Q2__bar $end
$var wire 1 }3 Q3__bar $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 ;3 in [0] $end
$var wire 1 ;$ in [1] $end
$var wire 1 =3 in [2] $end
$var wire 1 53 mem [0] $end
$var wire 1 63 mem [1] $end
$var wire 1 73 mem [2] $end
$var wire 1 83 mem_inv [0] $end
$var wire 1 93 mem_inv [1] $end
$var wire 1 :3 mem_inv [2] $end
$var wire 1 <3 out [0] $end
$var wire 1 (' p0 $end

$scope module scs8hd_muxinv3_1_0 $end
$var wire 1 <3 Z $end
$var wire 1 ;3 Q1 $end
$var wire 1 ;$ Q2 $end
$var wire 1 (' Q3 $end
$var wire 1 53 S0 $end
$var wire 1 83 S0B $end
$var wire 1 63 S1 $end
$var wire 1 93 S1B $end
$var wire 1 73 S2 $end
$var wire 1 :3 S2B $end
$var wire 1 ~3 Q1__bar $end
$var wire 1 !4 Q2__bar $end
$var wire 1 "4 Q3__bar $end
$upscope $end
$upscope $end

$scope module BINV_R_106 $end
$var wire 1 `$ Y $end
$var wire 1 >3 A $end
$var supply1 1 #4 VPWR $end
$var supply0 1 $4 VGND $end
$var supply1 1 %4 VPB $end
$var supply0 1 &4 VNB $end

$scope module base $end
$var wire 1 `$ Y $end
$var wire 1 >3 A $end
$var wire 1 '4 not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_107 $end
$var wire 1 >3 Y $end
$var wire 1 <3 A $end
$var supply1 1 (4 VPWR $end
$var supply0 1 )4 VGND $end
$var supply1 1 *4 VPB $end
$var supply0 1 +4 VNB $end

$scope module base $end
$var wire 1 >3 Y $end
$var wire 1 <3 A $end
$var wire 1 ,4 not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_1 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 <$ ccff_head [0] $end
$var wire 1 m& ccff_tail [0] $end
$var wire 1 =& mem_out [0] $end
$var wire 1 >& mem_out [1] $end
$var wire 1 ?& mem_out [2] $end
$var wire 1 @& mem_out [3] $end
$var wire 1 -4 ropt_net_200 $end
$var wire 1 .4 ropt_net_197 $end
$var wire 1 /4 ropt_net_201 $end
$var wire 1 04 ropt_net_198 $end
$var wire 1 14 ropt_net_199 $end
$var wire 1 24 ropt_net_202 $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 =& Q $end
$var wire 1 }$ CLK $end
$var wire 1 -4 D $end
$var wire 1 K# RESET_B $end
$var supply1 1 34 VPWR $end
$var supply0 1 44 VGND $end
$var supply1 1 54 VPB $end
$var supply0 1 64 VNB $end

$scope module base $end
$var wire 1 =& Q $end
$var wire 1 }$ CLK $end
$var wire 1 -4 D $end
$var wire 1 K# RESET_B $end
$var wire 1 74 buf_Q $end
$var wire 1 84 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 >& Q $end
$var wire 1 }$ CLK $end
$var wire 1 =& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 94 VPWR $end
$var supply0 1 :4 VGND $end
$var supply1 1 ;4 VPB $end
$var supply0 1 <4 VNB $end

$scope module base $end
$var wire 1 >& Q $end
$var wire 1 }$ CLK $end
$var wire 1 =& D $end
$var wire 1 K# RESET_B $end
$var wire 1 =4 buf_Q $end
$var wire 1 >4 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end
$var wire 1 ?& Q $end
$var wire 1 }$ CLK $end
$var wire 1 >& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 ?4 VPWR $end
$var supply0 1 @4 VGND $end
$var supply1 1 A4 VPB $end
$var supply0 1 B4 VNB $end

$scope module base $end
$var wire 1 ?& Q $end
$var wire 1 }$ CLK $end
$var wire 1 >& D $end
$var wire 1 K# RESET_B $end
$var wire 1 C4 buf_Q $end
$var wire 1 D4 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end
$var wire 1 @& Q $end
$var wire 1 }$ CLK $end
$var wire 1 ?& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 E4 VPWR $end
$var supply0 1 F4 VGND $end
$var supply1 1 G4 VPB $end
$var supply0 1 H4 VNB $end

$scope module base $end
$var wire 1 @& Q $end
$var wire 1 }$ CLK $end
$var wire 1 ?& D $end
$var wire 1 K# RESET_B $end
$var wire 1 I4 buf_Q $end
$var wire 1 J4 RESET $end
$upscope $end
$upscope $end

$scope module FTB_25__24 $end
$var wire 1 m& X $end
$var wire 1 @& A $end
$var supply1 1 K4 VPWR $end
$var supply0 1 L4 VGND $end
$var supply1 1 M4 VPB $end
$var supply0 1 N4 VNB $end

$scope module base $end
$var wire 1 m& X $end
$var wire 1 @& A $end
$var wire 1 O4 buf0_out_X $end
$upscope $end
$upscope $end

$scope module ropt_h_inst_1429 $end
$var wire 1 .4 X $end
$var wire 1 <$ A $end
$var supply1 1 P4 VPWR $end
$var supply0 1 Q4 VGND $end
$var supply1 1 R4 VPB $end
$var supply0 1 S4 VNB $end

$scope module base $end
$var wire 1 .4 X $end
$var wire 1 <$ A $end
$var wire 1 T4 buf0_out_X $end
$upscope $end
$upscope $end

$scope module ropt_h_inst_1430 $end
$var wire 1 04 X $end
$var wire 1 /4 A $end
$var supply1 1 U4 VPWR $end
$var supply0 1 V4 VGND $end
$var supply1 1 W4 VPB $end
$var supply0 1 X4 VNB $end

$scope module base $end
$var wire 1 04 X $end
$var wire 1 /4 A $end
$var wire 1 Y4 buf0_out_X $end
$upscope $end
$upscope $end

$scope module ropt_h_inst_1431 $end
$var wire 1 14 X $end
$var wire 1 04 A $end
$var supply1 1 Z4 VPWR $end
$var supply0 1 [4 VGND $end
$var supply1 1 \4 VPB $end
$var supply0 1 ]4 VNB $end

$scope module base $end
$var wire 1 14 X $end
$var wire 1 04 A $end
$var wire 1 ^4 buf0_out_X $end
$upscope $end
$upscope $end

$scope module ropt_h_inst_1432 $end
$var wire 1 -4 X $end
$var wire 1 14 A $end
$var supply1 1 _4 VPWR $end
$var supply0 1 `4 VGND $end
$var supply1 1 a4 VPB $end
$var supply0 1 b4 VNB $end

$scope module base $end
$var wire 1 -4 X $end
$var wire 1 14 A $end
$var wire 1 c4 buf0_out_X $end
$upscope $end
$upscope $end

$scope module ropt_h_inst_1433 $end
$var wire 1 /4 X $end
$var wire 1 24 A $end
$var supply1 1 d4 VPWR $end
$var supply0 1 e4 VGND $end
$var supply1 1 f4 VPB $end
$var supply0 1 g4 VNB $end

$scope module base $end
$var wire 1 /4 X $end
$var wire 1 24 A $end
$var wire 1 h4 buf0_out_X $end
$upscope $end
$upscope $end

$scope module ropt_h_inst_1434 $end
$var wire 1 24 X $end
$var wire 1 .4 A $end
$var supply1 1 i4 VPWR $end
$var supply0 1 j4 VGND $end
$var supply1 1 k4 VPB $end
$var supply0 1 l4 VNB $end

$scope module base $end
$var wire 1 24 X $end
$var wire 1 .4 A $end
$var wire 1 m4 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_3 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 m& ccff_head [0] $end
$var wire 1 p& ccff_tail [0] $end
$var wire 1 I& mem_out [0] $end
$var wire 1 J& mem_out [1] $end
$var wire 1 K& mem_out [2] $end
$var wire 1 L& mem_out [3] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 I& Q $end
$var wire 1 }$ CLK $end
$var wire 1 m& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 n4 VPWR $end
$var supply0 1 o4 VGND $end
$var supply1 1 p4 VPB $end
$var supply0 1 q4 VNB $end

$scope module base $end
$var wire 1 I& Q $end
$var wire 1 }$ CLK $end
$var wire 1 m& D $end
$var wire 1 K# RESET_B $end
$var wire 1 r4 buf_Q $end
$var wire 1 s4 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 J& Q $end
$var wire 1 }$ CLK $end
$var wire 1 I& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 t4 VPWR $end
$var supply0 1 u4 VGND $end
$var supply1 1 v4 VPB $end
$var supply0 1 w4 VNB $end

$scope module base $end
$var wire 1 J& Q $end
$var wire 1 }$ CLK $end
$var wire 1 I& D $end
$var wire 1 K# RESET_B $end
$var wire 1 x4 buf_Q $end
$var wire 1 y4 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end
$var wire 1 K& Q $end
$var wire 1 }$ CLK $end
$var wire 1 J& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 z4 VPWR $end
$var supply0 1 {4 VGND $end
$var supply1 1 |4 VPB $end
$var supply0 1 }4 VNB $end

$scope module base $end
$var wire 1 K& Q $end
$var wire 1 }$ CLK $end
$var wire 1 J& D $end
$var wire 1 K# RESET_B $end
$var wire 1 ~4 buf_Q $end
$var wire 1 !5 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end
$var wire 1 L& Q $end
$var wire 1 }$ CLK $end
$var wire 1 K& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 "5 VPWR $end
$var supply0 1 #5 VGND $end
$var supply1 1 $5 VPB $end
$var supply0 1 %5 VNB $end

$scope module base $end
$var wire 1 L& Q $end
$var wire 1 }$ CLK $end
$var wire 1 K& D $end
$var wire 1 K# RESET_B $end
$var wire 1 &5 buf_Q $end
$var wire 1 '5 RESET $end
$upscope $end
$upscope $end

$scope module FTB_26__25 $end
$var wire 1 p& X $end
$var wire 1 L& A $end
$var supply1 1 (5 VPWR $end
$var supply0 1 )5 VGND $end
$var supply1 1 *5 VPB $end
$var supply0 1 +5 VNB $end

$scope module base $end
$var wire 1 p& X $end
$var wire 1 L& A $end
$var wire 1 ,5 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_5 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 p& ccff_head [0] $end
$var wire 1 q& ccff_tail [0] $end
$var wire 1 M& mem_out [0] $end
$var wire 1 N& mem_out [1] $end
$var wire 1 O& mem_out [2] $end
$var wire 1 P& mem_out [3] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 M& Q $end
$var wire 1 }$ CLK $end
$var wire 1 p& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 -5 VPWR $end
$var supply0 1 .5 VGND $end
$var supply1 1 /5 VPB $end
$var supply0 1 05 VNB $end

$scope module base $end
$var wire 1 M& Q $end
$var wire 1 }$ CLK $end
$var wire 1 p& D $end
$var wire 1 K# RESET_B $end
$var wire 1 15 buf_Q $end
$var wire 1 25 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 N& Q $end
$var wire 1 }$ CLK $end
$var wire 1 M& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 35 VPWR $end
$var supply0 1 45 VGND $end
$var supply1 1 55 VPB $end
$var supply0 1 65 VNB $end

$scope module base $end
$var wire 1 N& Q $end
$var wire 1 }$ CLK $end
$var wire 1 M& D $end
$var wire 1 K# RESET_B $end
$var wire 1 75 buf_Q $end
$var wire 1 85 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end
$var wire 1 O& Q $end
$var wire 1 }$ CLK $end
$var wire 1 N& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 95 VPWR $end
$var supply0 1 :5 VGND $end
$var supply1 1 ;5 VPB $end
$var supply0 1 <5 VNB $end

$scope module base $end
$var wire 1 O& Q $end
$var wire 1 }$ CLK $end
$var wire 1 N& D $end
$var wire 1 K# RESET_B $end
$var wire 1 =5 buf_Q $end
$var wire 1 >5 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end
$var wire 1 P& Q $end
$var wire 1 }$ CLK $end
$var wire 1 O& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 ?5 VPWR $end
$var supply0 1 @5 VGND $end
$var supply1 1 A5 VPB $end
$var supply0 1 B5 VNB $end

$scope module base $end
$var wire 1 P& Q $end
$var wire 1 }$ CLK $end
$var wire 1 O& D $end
$var wire 1 K# RESET_B $end
$var wire 1 C5 buf_Q $end
$var wire 1 D5 RESET $end
$upscope $end
$upscope $end

$scope module FTB_27__26 $end
$var wire 1 q& X $end
$var wire 1 P& A $end
$var supply1 1 E5 VPWR $end
$var supply0 1 F5 VGND $end
$var supply1 1 G5 VPB $end
$var supply0 1 H5 VNB $end

$scope module base $end
$var wire 1 q& X $end
$var wire 1 P& A $end
$var wire 1 I5 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_7 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 q& ccff_head [0] $end
$var wire 1 r& ccff_tail [0] $end
$var wire 1 Q& mem_out [0] $end
$var wire 1 R& mem_out [1] $end
$var wire 1 S& mem_out [2] $end
$var wire 1 T& mem_out [3] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 Q& Q $end
$var wire 1 }$ CLK $end
$var wire 1 q& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 J5 VPWR $end
$var supply0 1 K5 VGND $end
$var supply1 1 L5 VPB $end
$var supply0 1 M5 VNB $end

$scope module base $end
$var wire 1 Q& Q $end
$var wire 1 }$ CLK $end
$var wire 1 q& D $end
$var wire 1 K# RESET_B $end
$var wire 1 N5 buf_Q $end
$var wire 1 O5 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 R& Q $end
$var wire 1 }$ CLK $end
$var wire 1 Q& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 P5 VPWR $end
$var supply0 1 Q5 VGND $end
$var supply1 1 R5 VPB $end
$var supply0 1 S5 VNB $end

$scope module base $end
$var wire 1 R& Q $end
$var wire 1 }$ CLK $end
$var wire 1 Q& D $end
$var wire 1 K# RESET_B $end
$var wire 1 T5 buf_Q $end
$var wire 1 U5 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end
$var wire 1 S& Q $end
$var wire 1 }$ CLK $end
$var wire 1 R& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 V5 VPWR $end
$var supply0 1 W5 VGND $end
$var supply1 1 X5 VPB $end
$var supply0 1 Y5 VNB $end

$scope module base $end
$var wire 1 S& Q $end
$var wire 1 }$ CLK $end
$var wire 1 R& D $end
$var wire 1 K# RESET_B $end
$var wire 1 Z5 buf_Q $end
$var wire 1 [5 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end
$var wire 1 T& Q $end
$var wire 1 }$ CLK $end
$var wire 1 S& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 \5 VPWR $end
$var supply0 1 ]5 VGND $end
$var supply1 1 ^5 VPB $end
$var supply0 1 _5 VNB $end

$scope module base $end
$var wire 1 T& Q $end
$var wire 1 }$ CLK $end
$var wire 1 S& D $end
$var wire 1 K# RESET_B $end
$var wire 1 `5 buf_Q $end
$var wire 1 a5 RESET $end
$upscope $end
$upscope $end

$scope module FTB_28__27 $end
$var wire 1 r& X $end
$var wire 1 T& A $end
$var supply1 1 b5 VPWR $end
$var supply0 1 c5 VGND $end
$var supply1 1 d5 VPB $end
$var supply0 1 e5 VNB $end

$scope module base $end
$var wire 1 r& X $end
$var wire 1 T& A $end
$var wire 1 f5 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_9 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 r& ccff_head [0] $end
$var wire 1 s& ccff_tail [0] $end
$var wire 1 U& mem_out [0] $end
$var wire 1 V& mem_out [1] $end
$var wire 1 W& mem_out [2] $end
$var wire 1 X& mem_out [3] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 U& Q $end
$var wire 1 }$ CLK $end
$var wire 1 r& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 g5 VPWR $end
$var supply0 1 h5 VGND $end
$var supply1 1 i5 VPB $end
$var supply0 1 j5 VNB $end

$scope module base $end
$var wire 1 U& Q $end
$var wire 1 }$ CLK $end
$var wire 1 r& D $end
$var wire 1 K# RESET_B $end
$var wire 1 k5 buf_Q $end
$var wire 1 l5 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 V& Q $end
$var wire 1 }$ CLK $end
$var wire 1 U& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 m5 VPWR $end
$var supply0 1 n5 VGND $end
$var supply1 1 o5 VPB $end
$var supply0 1 p5 VNB $end

$scope module base $end
$var wire 1 V& Q $end
$var wire 1 }$ CLK $end
$var wire 1 U& D $end
$var wire 1 K# RESET_B $end
$var wire 1 q5 buf_Q $end
$var wire 1 r5 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end
$var wire 1 W& Q $end
$var wire 1 }$ CLK $end
$var wire 1 V& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 s5 VPWR $end
$var supply0 1 t5 VGND $end
$var supply1 1 u5 VPB $end
$var supply0 1 v5 VNB $end

$scope module base $end
$var wire 1 W& Q $end
$var wire 1 }$ CLK $end
$var wire 1 V& D $end
$var wire 1 K# RESET_B $end
$var wire 1 w5 buf_Q $end
$var wire 1 x5 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end
$var wire 1 X& Q $end
$var wire 1 }$ CLK $end
$var wire 1 W& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 y5 VPWR $end
$var supply0 1 z5 VGND $end
$var supply1 1 {5 VPB $end
$var supply0 1 |5 VNB $end

$scope module base $end
$var wire 1 X& Q $end
$var wire 1 }$ CLK $end
$var wire 1 W& D $end
$var wire 1 K# RESET_B $end
$var wire 1 }5 buf_Q $end
$var wire 1 ~5 RESET $end
$upscope $end
$upscope $end

$scope module FTB_29__28 $end
$var wire 1 s& X $end
$var wire 1 X& A $end
$var supply1 1 !6 VPWR $end
$var supply0 1 "6 VGND $end
$var supply1 1 #6 VPB $end
$var supply0 1 $6 VNB $end

$scope module base $end
$var wire 1 s& X $end
$var wire 1 X& A $end
$var wire 1 %6 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_11 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 s& ccff_head [0] $end
$var wire 1 t& ccff_tail [0] $end
$var wire 1 Y& mem_out [0] $end
$var wire 1 Z& mem_out [1] $end
$var wire 1 [& mem_out [2] $end
$var wire 1 \& mem_out [3] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 Y& Q $end
$var wire 1 }$ CLK $end
$var wire 1 s& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 &6 VPWR $end
$var supply0 1 '6 VGND $end
$var supply1 1 (6 VPB $end
$var supply0 1 )6 VNB $end

$scope module base $end
$var wire 1 Y& Q $end
$var wire 1 }$ CLK $end
$var wire 1 s& D $end
$var wire 1 K# RESET_B $end
$var wire 1 *6 buf_Q $end
$var wire 1 +6 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 Z& Q $end
$var wire 1 }$ CLK $end
$var wire 1 Y& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 ,6 VPWR $end
$var supply0 1 -6 VGND $end
$var supply1 1 .6 VPB $end
$var supply0 1 /6 VNB $end

$scope module base $end
$var wire 1 Z& Q $end
$var wire 1 }$ CLK $end
$var wire 1 Y& D $end
$var wire 1 K# RESET_B $end
$var wire 1 06 buf_Q $end
$var wire 1 16 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end
$var wire 1 [& Q $end
$var wire 1 }$ CLK $end
$var wire 1 Z& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 26 VPWR $end
$var supply0 1 36 VGND $end
$var supply1 1 46 VPB $end
$var supply0 1 56 VNB $end

$scope module base $end
$var wire 1 [& Q $end
$var wire 1 }$ CLK $end
$var wire 1 Z& D $end
$var wire 1 K# RESET_B $end
$var wire 1 66 buf_Q $end
$var wire 1 76 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end
$var wire 1 \& Q $end
$var wire 1 }$ CLK $end
$var wire 1 [& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 86 VPWR $end
$var supply0 1 96 VGND $end
$var supply1 1 :6 VPB $end
$var supply0 1 ;6 VNB $end

$scope module base $end
$var wire 1 \& Q $end
$var wire 1 }$ CLK $end
$var wire 1 [& D $end
$var wire 1 K# RESET_B $end
$var wire 1 <6 buf_Q $end
$var wire 1 =6 RESET $end
$upscope $end
$upscope $end

$scope module FTB_30__29 $end
$var wire 1 t& X $end
$var wire 1 \& A $end
$var supply1 1 >6 VPWR $end
$var supply0 1 ?6 VGND $end
$var supply1 1 @6 VPB $end
$var supply0 1 A6 VNB $end

$scope module base $end
$var wire 1 t& X $end
$var wire 1 \& A $end
$var wire 1 B6 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_1 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 p% ccff_head [0] $end
$var wire 1 u& ccff_tail [0] $end
$var wire 1 ]& mem_out [0] $end
$var wire 1 ^& mem_out [1] $end
$var wire 1 _& mem_out [2] $end
$var wire 1 `& mem_out [3] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 ]& Q $end
$var wire 1 }$ CLK $end
$var wire 1 p% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 C6 VPWR $end
$var supply0 1 D6 VGND $end
$var supply1 1 E6 VPB $end
$var supply0 1 F6 VNB $end

$scope module base $end
$var wire 1 ]& Q $end
$var wire 1 }$ CLK $end
$var wire 1 p% D $end
$var wire 1 K# RESET_B $end
$var wire 1 G6 buf_Q $end
$var wire 1 H6 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 ^& Q $end
$var wire 1 }$ CLK $end
$var wire 1 ]& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 I6 VPWR $end
$var supply0 1 J6 VGND $end
$var supply1 1 K6 VPB $end
$var supply0 1 L6 VNB $end

$scope module base $end
$var wire 1 ^& Q $end
$var wire 1 }$ CLK $end
$var wire 1 ]& D $end
$var wire 1 K# RESET_B $end
$var wire 1 M6 buf_Q $end
$var wire 1 N6 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end
$var wire 1 _& Q $end
$var wire 1 }$ CLK $end
$var wire 1 ^& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 O6 VPWR $end
$var supply0 1 P6 VGND $end
$var supply1 1 Q6 VPB $end
$var supply0 1 R6 VNB $end

$scope module base $end
$var wire 1 _& Q $end
$var wire 1 }$ CLK $end
$var wire 1 ^& D $end
$var wire 1 K# RESET_B $end
$var wire 1 S6 buf_Q $end
$var wire 1 T6 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end
$var wire 1 `& Q $end
$var wire 1 }$ CLK $end
$var wire 1 _& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 U6 VPWR $end
$var supply0 1 V6 VGND $end
$var supply1 1 W6 VPB $end
$var supply0 1 X6 VNB $end

$scope module base $end
$var wire 1 `& Q $end
$var wire 1 }$ CLK $end
$var wire 1 _& D $end
$var wire 1 K# RESET_B $end
$var wire 1 Y6 buf_Q $end
$var wire 1 Z6 RESET $end
$upscope $end
$upscope $end

$scope module FTB_31__30 $end
$var wire 1 u& X $end
$var wire 1 `& A $end
$var supply1 1 [6 VPWR $end
$var supply0 1 \6 VGND $end
$var supply1 1 ]6 VPB $end
$var supply0 1 ^6 VNB $end

$scope module base $end
$var wire 1 u& X $end
$var wire 1 `& A $end
$var wire 1 _6 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_3 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 u& ccff_head [0] $end
$var wire 1 v& ccff_tail [0] $end
$var wire 1 a& mem_out [0] $end
$var wire 1 b& mem_out [1] $end
$var wire 1 c& mem_out [2] $end
$var wire 1 d& mem_out [3] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 a& Q $end
$var wire 1 }$ CLK $end
$var wire 1 u& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 `6 VPWR $end
$var supply0 1 a6 VGND $end
$var supply1 1 b6 VPB $end
$var supply0 1 c6 VNB $end

$scope module base $end
$var wire 1 a& Q $end
$var wire 1 }$ CLK $end
$var wire 1 u& D $end
$var wire 1 K# RESET_B $end
$var wire 1 d6 buf_Q $end
$var wire 1 e6 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 b& Q $end
$var wire 1 }$ CLK $end
$var wire 1 a& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 f6 VPWR $end
$var supply0 1 g6 VGND $end
$var supply1 1 h6 VPB $end
$var supply0 1 i6 VNB $end

$scope module base $end
$var wire 1 b& Q $end
$var wire 1 }$ CLK $end
$var wire 1 a& D $end
$var wire 1 K# RESET_B $end
$var wire 1 j6 buf_Q $end
$var wire 1 k6 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end
$var wire 1 c& Q $end
$var wire 1 }$ CLK $end
$var wire 1 b& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 l6 VPWR $end
$var supply0 1 m6 VGND $end
$var supply1 1 n6 VPB $end
$var supply0 1 o6 VNB $end

$scope module base $end
$var wire 1 c& Q $end
$var wire 1 }$ CLK $end
$var wire 1 b& D $end
$var wire 1 K# RESET_B $end
$var wire 1 p6 buf_Q $end
$var wire 1 q6 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end
$var wire 1 d& Q $end
$var wire 1 }$ CLK $end
$var wire 1 c& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 r6 VPWR $end
$var supply0 1 s6 VGND $end
$var supply1 1 t6 VPB $end
$var supply0 1 u6 VNB $end

$scope module base $end
$var wire 1 d& Q $end
$var wire 1 }$ CLK $end
$var wire 1 c& D $end
$var wire 1 K# RESET_B $end
$var wire 1 v6 buf_Q $end
$var wire 1 w6 RESET $end
$upscope $end
$upscope $end

$scope module FTB_32__31 $end
$var wire 1 v& X $end
$var wire 1 d& A $end
$var supply1 1 x6 VPWR $end
$var supply0 1 y6 VGND $end
$var supply1 1 z6 VPB $end
$var supply0 1 {6 VNB $end

$scope module base $end
$var wire 1 v& X $end
$var wire 1 d& A $end
$var wire 1 |6 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_5 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 v& ccff_head [0] $end
$var wire 1 w& ccff_tail [0] $end
$var wire 1 e& mem_out [0] $end
$var wire 1 f& mem_out [1] $end
$var wire 1 g& mem_out [2] $end
$var wire 1 h& mem_out [3] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 e& Q $end
$var wire 1 }$ CLK $end
$var wire 1 v& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 }6 VPWR $end
$var supply0 1 ~6 VGND $end
$var supply1 1 !7 VPB $end
$var supply0 1 "7 VNB $end

$scope module base $end
$var wire 1 e& Q $end
$var wire 1 }$ CLK $end
$var wire 1 v& D $end
$var wire 1 K# RESET_B $end
$var wire 1 #7 buf_Q $end
$var wire 1 $7 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 f& Q $end
$var wire 1 }$ CLK $end
$var wire 1 e& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 %7 VPWR $end
$var supply0 1 &7 VGND $end
$var supply1 1 '7 VPB $end
$var supply0 1 (7 VNB $end

$scope module base $end
$var wire 1 f& Q $end
$var wire 1 }$ CLK $end
$var wire 1 e& D $end
$var wire 1 K# RESET_B $end
$var wire 1 )7 buf_Q $end
$var wire 1 *7 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end
$var wire 1 g& Q $end
$var wire 1 }$ CLK $end
$var wire 1 f& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 +7 VPWR $end
$var supply0 1 ,7 VGND $end
$var supply1 1 -7 VPB $end
$var supply0 1 .7 VNB $end

$scope module base $end
$var wire 1 g& Q $end
$var wire 1 }$ CLK $end
$var wire 1 f& D $end
$var wire 1 K# RESET_B $end
$var wire 1 /7 buf_Q $end
$var wire 1 07 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end
$var wire 1 h& Q $end
$var wire 1 }$ CLK $end
$var wire 1 g& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 17 VPWR $end
$var supply0 1 27 VGND $end
$var supply1 1 37 VPB $end
$var supply0 1 47 VNB $end

$scope module base $end
$var wire 1 h& Q $end
$var wire 1 }$ CLK $end
$var wire 1 g& D $end
$var wire 1 K# RESET_B $end
$var wire 1 57 buf_Q $end
$var wire 1 67 RESET $end
$upscope $end
$upscope $end

$scope module FTB_33__32 $end
$var wire 1 w& X $end
$var wire 1 h& A $end
$var supply1 1 77 VPWR $end
$var supply0 1 87 VGND $end
$var supply1 1 97 VPB $end
$var supply0 1 :7 VNB $end

$scope module base $end
$var wire 1 w& X $end
$var wire 1 h& A $end
$var wire 1 ;7 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_7 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 w& ccff_head [0] $end
$var wire 1 x& ccff_tail [0] $end
$var wire 1 i& mem_out [0] $end
$var wire 1 j& mem_out [1] $end
$var wire 1 k& mem_out [2] $end
$var wire 1 l& mem_out [3] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 i& Q $end
$var wire 1 }$ CLK $end
$var wire 1 w& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 <7 VPWR $end
$var supply0 1 =7 VGND $end
$var supply1 1 >7 VPB $end
$var supply0 1 ?7 VNB $end

$scope module base $end
$var wire 1 i& Q $end
$var wire 1 }$ CLK $end
$var wire 1 w& D $end
$var wire 1 K# RESET_B $end
$var wire 1 @7 buf_Q $end
$var wire 1 A7 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 j& Q $end
$var wire 1 }$ CLK $end
$var wire 1 i& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 B7 VPWR $end
$var supply0 1 C7 VGND $end
$var supply1 1 D7 VPB $end
$var supply0 1 E7 VNB $end

$scope module base $end
$var wire 1 j& Q $end
$var wire 1 }$ CLK $end
$var wire 1 i& D $end
$var wire 1 K# RESET_B $end
$var wire 1 F7 buf_Q $end
$var wire 1 G7 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end
$var wire 1 k& Q $end
$var wire 1 }$ CLK $end
$var wire 1 j& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 H7 VPWR $end
$var supply0 1 I7 VGND $end
$var supply1 1 J7 VPB $end
$var supply0 1 K7 VNB $end

$scope module base $end
$var wire 1 k& Q $end
$var wire 1 }$ CLK $end
$var wire 1 j& D $end
$var wire 1 K# RESET_B $end
$var wire 1 L7 buf_Q $end
$var wire 1 M7 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end
$var wire 1 l& Q $end
$var wire 1 }$ CLK $end
$var wire 1 k& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 N7 VPWR $end
$var supply0 1 O7 VGND $end
$var supply1 1 P7 VPB $end
$var supply0 1 Q7 VNB $end

$scope module base $end
$var wire 1 l& Q $end
$var wire 1 }$ CLK $end
$var wire 1 k& D $end
$var wire 1 K# RESET_B $end
$var wire 1 R7 buf_Q $end
$var wire 1 S7 RESET $end
$upscope $end
$upscope $end

$scope module FTB_34__33 $end
$var wire 1 x& X $end
$var wire 1 l& A $end
$var supply1 1 T7 VPWR $end
$var supply0 1 U7 VGND $end
$var supply1 1 V7 VPB $end
$var supply0 1 W7 VNB $end

$scope module base $end
$var wire 1 x& X $end
$var wire 1 l& A $end
$var wire 1 X7 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_9 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 x& ccff_head [0] $end
$var wire 1 n& ccff_tail [0] $end
$var wire 1 A& mem_out [0] $end
$var wire 1 B& mem_out [1] $end
$var wire 1 C& mem_out [2] $end
$var wire 1 D& mem_out [3] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 A& Q $end
$var wire 1 }$ CLK $end
$var wire 1 x& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 Y7 VPWR $end
$var supply0 1 Z7 VGND $end
$var supply1 1 [7 VPB $end
$var supply0 1 \7 VNB $end

$scope module base $end
$var wire 1 A& Q $end
$var wire 1 }$ CLK $end
$var wire 1 x& D $end
$var wire 1 K# RESET_B $end
$var wire 1 ]7 buf_Q $end
$var wire 1 ^7 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 B& Q $end
$var wire 1 }$ CLK $end
$var wire 1 A& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 _7 VPWR $end
$var supply0 1 `7 VGND $end
$var supply1 1 a7 VPB $end
$var supply0 1 b7 VNB $end

$scope module base $end
$var wire 1 B& Q $end
$var wire 1 }$ CLK $end
$var wire 1 A& D $end
$var wire 1 K# RESET_B $end
$var wire 1 c7 buf_Q $end
$var wire 1 d7 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end
$var wire 1 C& Q $end
$var wire 1 }$ CLK $end
$var wire 1 B& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 e7 VPWR $end
$var supply0 1 f7 VGND $end
$var supply1 1 g7 VPB $end
$var supply0 1 h7 VNB $end

$scope module base $end
$var wire 1 C& Q $end
$var wire 1 }$ CLK $end
$var wire 1 B& D $end
$var wire 1 K# RESET_B $end
$var wire 1 i7 buf_Q $end
$var wire 1 j7 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end
$var wire 1 D& Q $end
$var wire 1 }$ CLK $end
$var wire 1 C& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 k7 VPWR $end
$var supply0 1 l7 VGND $end
$var supply1 1 m7 VPB $end
$var supply0 1 n7 VNB $end

$scope module base $end
$var wire 1 D& Q $end
$var wire 1 }$ CLK $end
$var wire 1 C& D $end
$var wire 1 K# RESET_B $end
$var wire 1 o7 buf_Q $end
$var wire 1 p7 RESET $end
$upscope $end
$upscope $end

$scope module FTB_35__34 $end
$var wire 1 n& X $end
$var wire 1 D& A $end
$var supply1 1 q7 VPWR $end
$var supply0 1 r7 VGND $end
$var supply1 1 s7 VPB $end
$var supply0 1 t7 VNB $end

$scope module base $end
$var wire 1 n& X $end
$var wire 1 D& A $end
$var wire 1 u7 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_11 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 n& ccff_head [0] $end
$var wire 1 o& ccff_tail [0] $end
$var wire 1 E& mem_out [0] $end
$var wire 1 F& mem_out [1] $end
$var wire 1 G& mem_out [2] $end
$var wire 1 H& mem_out [3] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 E& Q $end
$var wire 1 }$ CLK $end
$var wire 1 n& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 v7 VPWR $end
$var supply0 1 w7 VGND $end
$var supply1 1 x7 VPB $end
$var supply0 1 y7 VNB $end

$scope module base $end
$var wire 1 E& Q $end
$var wire 1 }$ CLK $end
$var wire 1 n& D $end
$var wire 1 K# RESET_B $end
$var wire 1 z7 buf_Q $end
$var wire 1 {7 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 F& Q $end
$var wire 1 }$ CLK $end
$var wire 1 E& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 |7 VPWR $end
$var supply0 1 }7 VGND $end
$var supply1 1 ~7 VPB $end
$var supply0 1 !8 VNB $end

$scope module base $end
$var wire 1 F& Q $end
$var wire 1 }$ CLK $end
$var wire 1 E& D $end
$var wire 1 K# RESET_B $end
$var wire 1 "8 buf_Q $end
$var wire 1 #8 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_2_ $end
$var wire 1 G& Q $end
$var wire 1 }$ CLK $end
$var wire 1 F& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 $8 VPWR $end
$var supply0 1 %8 VGND $end
$var supply1 1 &8 VPB $end
$var supply0 1 '8 VNB $end

$scope module base $end
$var wire 1 G& Q $end
$var wire 1 }$ CLK $end
$var wire 1 F& D $end
$var wire 1 K# RESET_B $end
$var wire 1 (8 buf_Q $end
$var wire 1 )8 RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_3_ $end
$var wire 1 H& Q $end
$var wire 1 }$ CLK $end
$var wire 1 G& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 *8 VPWR $end
$var supply0 1 +8 VGND $end
$var supply1 1 ,8 VPB $end
$var supply0 1 -8 VNB $end

$scope module base $end
$var wire 1 H& Q $end
$var wire 1 }$ CLK $end
$var wire 1 G& D $end
$var wire 1 K# RESET_B $end
$var wire 1 .8 buf_Q $end
$var wire 1 /8 RESET $end
$upscope $end
$upscope $end

$scope module FTB_36__35 $end
$var wire 1 o& X $end
$var wire 1 H& A $end
$var supply1 1 08 VPWR $end
$var supply0 1 18 VGND $end
$var supply1 1 28 VPB $end
$var supply0 1 38 VNB $end

$scope module base $end
$var wire 1 o& X $end
$var wire 1 H& A $end
$var wire 1 48 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_13 $end
$var wire 1 j# in [0] $end
$var wire 1 z# in [1] $end
$var wire 1 !% sram [0] $end
$var wire 1 "% sram [1] $end
$var wire 1 N' sram_inv [0] $end
$var wire 1 O' sram_inv [1] $end
$var wire 1 C$ out [0] $end
$var wire 1 1' p0 $end
$var wire 1 58 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 68 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 78 SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 88 SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 98 SYNOPSYS_UNCONNECTED_3 $end

$scope module mux_l1_in_0_ $end
$var wire 1 j# in [0] $end
$var wire 1 z# in [1] $end
$var wire 1 !% mem [0] $end
$var wire 1 78 mem_inv [0] $end
$var wire 1 58 out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 58 X $end
$var wire 1 z# A0 $end
$var wire 1 j# A1 $end
$var wire 1 !% S $end
$var supply1 1 :8 VPWR $end
$var supply0 1 ;8 VGND $end
$var supply1 1 <8 VPB $end
$var supply0 1 =8 VNB $end

$scope module base $end
$var wire 1 58 X $end
$var wire 1 z# A0 $end
$var wire 1 j# A1 $end
$var wire 1 !% S $end
$var wire 1 >8 mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 58 in [0] $end
$var wire 1 88 in [1] $end
$var wire 1 "% mem [0] $end
$var wire 1 98 mem_inv [0] $end
$var wire 1 68 out [0] $end
$var wire 1 1' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 68 X $end
$var wire 1 1' A0 $end
$var wire 1 58 A1 $end
$var wire 1 "% S $end
$var supply1 1 ?8 VPWR $end
$var supply0 1 @8 VGND $end
$var supply1 1 A8 VPB $end
$var supply0 1 B8 VNB $end

$scope module base $end
$var wire 1 68 X $end
$var wire 1 1' A0 $end
$var wire 1 58 A1 $end
$var wire 1 "% S $end
$var wire 1 C8 mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BUFT_RR_108 $end
$var wire 1 C$ X $end
$var wire 1 68 A $end
$var supply1 1 D8 VPWR $end
$var supply0 1 E8 VGND $end
$var supply1 1 F8 VPB $end
$var supply0 1 G8 VNB $end

$scope module base $end
$var wire 1 C$ X $end
$var wire 1 68 A $end
$var wire 1 H8 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_15 $end
$var wire 1 k# in [0] $end
$var wire 1 {# in [1] $end
$var wire 1 7% sram [0] $end
$var wire 1 8% sram [1] $end
$var wire 1 P' sram_inv [0] $end
$var wire 1 Q' sram_inv [1] $end
$var wire 1 D$ out [0] $end
$var wire 1 R' p0 $end
$var wire 1 I8 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 J8 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 K8 SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 L8 SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 M8 SYNOPSYS_UNCONNECTED_3 $end

$scope module mux_l1_in_0_ $end
$var wire 1 k# in [0] $end
$var wire 1 {# in [1] $end
$var wire 1 7% mem [0] $end
$var wire 1 K8 mem_inv [0] $end
$var wire 1 I8 out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 I8 X $end
$var wire 1 {# A0 $end
$var wire 1 k# A1 $end
$var wire 1 7% S $end
$var supply1 1 N8 VPWR $end
$var supply0 1 O8 VGND $end
$var supply1 1 P8 VPB $end
$var supply0 1 Q8 VNB $end

$scope module base $end
$var wire 1 I8 X $end
$var wire 1 {# A0 $end
$var wire 1 k# A1 $end
$var wire 1 7% S $end
$var wire 1 R8 mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 I8 in [0] $end
$var wire 1 L8 in [1] $end
$var wire 1 8% mem [0] $end
$var wire 1 M8 mem_inv [0] $end
$var wire 1 J8 out [0] $end
$var wire 1 R' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 J8 X $end
$var wire 1 R' A0 $end
$var wire 1 I8 A1 $end
$var wire 1 8% S $end
$var supply1 1 S8 VPWR $end
$var supply0 1 T8 VGND $end
$var supply1 1 U8 VPB $end
$var supply0 1 V8 VNB $end

$scope module base $end
$var wire 1 J8 X $end
$var wire 1 R' A0 $end
$var wire 1 I8 A1 $end
$var wire 1 8% S $end
$var wire 1 W8 mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BUFT_RR_109 $end
$var wire 1 D$ X $end
$var wire 1 J8 A $end
$var supply1 1 X8 VPWR $end
$var supply0 1 Y8 VGND $end
$var supply1 1 Z8 VPB $end
$var supply0 1 [8 VNB $end

$scope module base $end
$var wire 1 D$ X $end
$var wire 1 J8 A $end
$var wire 1 \8 buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_17 $end
$var wire 1 l# in [0] $end
$var wire 1 |# in [1] $end
$var wire 1 M% sram [0] $end
$var wire 1 N% sram [1] $end
$var wire 1 S' sram_inv [0] $end
$var wire 1 T' sram_inv [1] $end
$var wire 1 E$ out [0] $end
$var wire 1 R' p0 $end
$var wire 1 ]8 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 ^8 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 _8 SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 `8 SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 a8 SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 b8 BUF_net_111 $end

$scope module mux_l1_in_0_ $end
$var wire 1 l# in [0] $end
$var wire 1 |# in [1] $end
$var wire 1 M% mem [0] $end
$var wire 1 _8 mem_inv [0] $end
$var wire 1 ]8 out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 ]8 X $end
$var wire 1 |# A0 $end
$var wire 1 l# A1 $end
$var wire 1 M% S $end
$var supply1 1 c8 VPWR $end
$var supply0 1 d8 VGND $end
$var supply1 1 e8 VPB $end
$var supply0 1 f8 VNB $end

$scope module base $end
$var wire 1 ]8 X $end
$var wire 1 |# A0 $end
$var wire 1 l# A1 $end
$var wire 1 M% S $end
$var wire 1 g8 mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 ]8 in [0] $end
$var wire 1 `8 in [1] $end
$var wire 1 N% mem [0] $end
$var wire 1 a8 mem_inv [0] $end
$var wire 1 ^8 out [0] $end
$var wire 1 R' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 ^8 X $end
$var wire 1 R' A0 $end
$var wire 1 ]8 A1 $end
$var wire 1 N% S $end
$var supply1 1 h8 VPWR $end
$var supply0 1 i8 VGND $end
$var supply1 1 j8 VPB $end
$var supply0 1 k8 VNB $end

$scope module base $end
$var wire 1 ^8 X $end
$var wire 1 R' A0 $end
$var wire 1 ]8 A1 $end
$var wire 1 N% S $end
$var wire 1 l8 mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_110 $end
$var wire 1 E$ Y $end
$var wire 1 b8 A $end
$var supply1 1 m8 VPWR $end
$var supply0 1 n8 VGND $end
$var supply1 1 o8 VPB $end
$var supply0 1 p8 VNB $end

$scope module base $end
$var wire 1 E$ Y $end
$var wire 1 b8 A $end
$var wire 1 q8 not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_111 $end
$var wire 1 b8 Y $end
$var wire 1 ^8 A $end
$var supply1 1 r8 VPWR $end
$var supply0 1 s8 VGND $end
$var supply1 1 t8 VPB $end
$var supply0 1 u8 VNB $end

$scope module base $end
$var wire 1 b8 Y $end
$var wire 1 ^8 A $end
$var wire 1 v8 not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_19 $end
$var wire 1 m# in [0] $end
$var wire 1 }# in [1] $end
$var wire 1 ]% sram [0] $end
$var wire 1 ^% sram [1] $end
$var wire 1 U' sram_inv [0] $end
$var wire 1 V' sram_inv [1] $end
$var wire 1 F$ out [0] $end
$var wire 1 R' p0 $end
$var wire 1 w8 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 x8 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 y8 SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 z8 SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 {8 SYNOPSYS_UNCONNECTED_3 $end

$scope module sky130_fd_sc_hd__buf_4_0_ $end
$var wire 1 F$ X $end
$var wire 1 x8 A $end
$var supply1 1 |8 VPWR $end
$var supply0 1 }8 VGND $end
$var supply1 1 ~8 VPB $end
$var supply0 1 !9 VNB $end

$scope module base $end
$var wire 1 F$ X $end
$var wire 1 x8 A $end
$var wire 1 "9 buf0_out_X $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 m# in [0] $end
$var wire 1 }# in [1] $end
$var wire 1 ]% mem [0] $end
$var wire 1 y8 mem_inv [0] $end
$var wire 1 w8 out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 w8 X $end
$var wire 1 }# A0 $end
$var wire 1 m# A1 $end
$var wire 1 ]% S $end
$var supply1 1 #9 VPWR $end
$var supply0 1 $9 VGND $end
$var supply1 1 %9 VPB $end
$var supply0 1 &9 VNB $end

$scope module base $end
$var wire 1 w8 X $end
$var wire 1 }# A0 $end
$var wire 1 m# A1 $end
$var wire 1 ]% S $end
$var wire 1 '9 mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 w8 in [0] $end
$var wire 1 z8 in [1] $end
$var wire 1 ^% mem [0] $end
$var wire 1 {8 mem_inv [0] $end
$var wire 1 x8 out [0] $end
$var wire 1 R' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 x8 X $end
$var wire 1 R' A0 $end
$var wire 1 w8 A1 $end
$var wire 1 ^% S $end
$var supply1 1 (9 VPWR $end
$var supply0 1 )9 VGND $end
$var supply1 1 *9 VPB $end
$var supply0 1 +9 VNB $end

$scope module base $end
$var wire 1 x8 X $end
$var wire 1 R' A0 $end
$var wire 1 w8 A1 $end
$var wire 1 ^% S $end
$var wire 1 ,9 mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_21 $end
$var wire 1 n# in [0] $end
$var wire 1 ~# in [1] $end
$var wire 1 _% sram [0] $end
$var wire 1 `% sram [1] $end
$var wire 1 W' sram_inv [0] $end
$var wire 1 X' sram_inv [1] $end
$var wire 1 G$ out [0] $end
$var wire 1 Y' p0 $end
$var wire 1 -9 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 .9 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 /9 SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 09 SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 19 SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 29 BUF_net_113 $end

$scope module mux_l1_in_0_ $end
$var wire 1 n# in [0] $end
$var wire 1 ~# in [1] $end
$var wire 1 _% mem [0] $end
$var wire 1 /9 mem_inv [0] $end
$var wire 1 -9 out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 -9 X $end
$var wire 1 ~# A0 $end
$var wire 1 n# A1 $end
$var wire 1 _% S $end
$var supply1 1 39 VPWR $end
$var supply0 1 49 VGND $end
$var supply1 1 59 VPB $end
$var supply0 1 69 VNB $end

$scope module base $end
$var wire 1 -9 X $end
$var wire 1 ~# A0 $end
$var wire 1 n# A1 $end
$var wire 1 _% S $end
$var wire 1 79 mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 -9 in [0] $end
$var wire 1 09 in [1] $end
$var wire 1 `% mem [0] $end
$var wire 1 19 mem_inv [0] $end
$var wire 1 .9 out [0] $end
$var wire 1 Y' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 .9 X $end
$var wire 1 Y' A0 $end
$var wire 1 -9 A1 $end
$var wire 1 `% S $end
$var supply1 1 89 VPWR $end
$var supply0 1 99 VGND $end
$var supply1 1 :9 VPB $end
$var supply0 1 ;9 VNB $end

$scope module base $end
$var wire 1 .9 X $end
$var wire 1 Y' A0 $end
$var wire 1 -9 A1 $end
$var wire 1 `% S $end
$var wire 1 <9 mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_112 $end
$var wire 1 G$ Y $end
$var wire 1 29 A $end
$var supply1 1 =9 VPWR $end
$var supply0 1 >9 VGND $end
$var supply1 1 ?9 VPB $end
$var supply0 1 @9 VNB $end

$scope module base $end
$var wire 1 G$ Y $end
$var wire 1 29 A $end
$var wire 1 A9 not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_113 $end
$var wire 1 29 Y $end
$var wire 1 .9 A $end
$var supply1 1 B9 VPWR $end
$var supply0 1 C9 VGND $end
$var supply1 1 D9 VPB $end
$var supply0 1 E9 VNB $end

$scope module base $end
$var wire 1 29 Y $end
$var wire 1 .9 A $end
$var wire 1 F9 not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_23 $end
$var wire 1 o# in [0] $end
$var wire 1 !$ in [1] $end
$var wire 1 a% sram [0] $end
$var wire 1 b% sram [1] $end
$var wire 1 Z' sram_inv [0] $end
$var wire 1 [' sram_inv [1] $end
$var wire 1 H$ out [0] $end
$var wire 1 Y' p0 $end
$var wire 1 G9 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 H9 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 I9 SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 J9 SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 K9 SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 L9 BUF_net_115 $end

$scope module mux_l1_in_0_ $end
$var wire 1 o# in [0] $end
$var wire 1 !$ in [1] $end
$var wire 1 a% mem [0] $end
$var wire 1 I9 mem_inv [0] $end
$var wire 1 G9 out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 G9 X $end
$var wire 1 !$ A0 $end
$var wire 1 o# A1 $end
$var wire 1 a% S $end
$var supply1 1 M9 VPWR $end
$var supply0 1 N9 VGND $end
$var supply1 1 O9 VPB $end
$var supply0 1 P9 VNB $end

$scope module base $end
$var wire 1 G9 X $end
$var wire 1 !$ A0 $end
$var wire 1 o# A1 $end
$var wire 1 a% S $end
$var wire 1 Q9 mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 G9 in [0] $end
$var wire 1 J9 in [1] $end
$var wire 1 b% mem [0] $end
$var wire 1 K9 mem_inv [0] $end
$var wire 1 H9 out [0] $end
$var wire 1 Y' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 H9 X $end
$var wire 1 Y' A0 $end
$var wire 1 G9 A1 $end
$var wire 1 b% S $end
$var supply1 1 R9 VPWR $end
$var supply0 1 S9 VGND $end
$var supply1 1 T9 VPB $end
$var supply0 1 U9 VNB $end

$scope module base $end
$var wire 1 H9 X $end
$var wire 1 Y' A0 $end
$var wire 1 G9 A1 $end
$var wire 1 b% S $end
$var wire 1 V9 mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_114 $end
$var wire 1 H$ Y $end
$var wire 1 L9 A $end
$var supply1 1 W9 VPWR $end
$var supply0 1 X9 VGND $end
$var supply1 1 Y9 VPB $end
$var supply0 1 Z9 VNB $end

$scope module base $end
$var wire 1 H$ Y $end
$var wire 1 L9 A $end
$var wire 1 [9 not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_115 $end
$var wire 1 L9 Y $end
$var wire 1 H9 A $end
$var supply1 1 \9 VPWR $end
$var supply0 1 ]9 VGND $end
$var supply1 1 ^9 VPB $end
$var supply0 1 _9 VNB $end

$scope module base $end
$var wire 1 L9 Y $end
$var wire 1 H9 A $end
$var wire 1 `9 not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_25 $end
$var wire 1 p# in [0] $end
$var wire 1 "$ in [1] $end
$var wire 1 c% sram [0] $end
$var wire 1 d% sram [1] $end
$var wire 1 \' sram_inv [0] $end
$var wire 1 ]' sram_inv [1] $end
$var wire 1 I$ out [0] $end
$var wire 1 }& p0 $end
$var wire 1 a9 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 b9 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 c9 SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 d9 SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 e9 SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 f9 BUF_net_117 $end

$scope module mux_l1_in_0_ $end
$var wire 1 p# in [0] $end
$var wire 1 "$ in [1] $end
$var wire 1 c% mem [0] $end
$var wire 1 c9 mem_inv [0] $end
$var wire 1 a9 out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 a9 X $end
$var wire 1 "$ A0 $end
$var wire 1 p# A1 $end
$var wire 1 c% S $end
$var supply1 1 g9 VPWR $end
$var supply0 1 h9 VGND $end
$var supply1 1 i9 VPB $end
$var supply0 1 j9 VNB $end

$scope module base $end
$var wire 1 a9 X $end
$var wire 1 "$ A0 $end
$var wire 1 p# A1 $end
$var wire 1 c% S $end
$var wire 1 k9 mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 a9 in [0] $end
$var wire 1 d9 in [1] $end
$var wire 1 d% mem [0] $end
$var wire 1 e9 mem_inv [0] $end
$var wire 1 b9 out [0] $end
$var wire 1 }& p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 b9 X $end
$var wire 1 }& A0 $end
$var wire 1 a9 A1 $end
$var wire 1 d% S $end
$var supply1 1 l9 VPWR $end
$var supply0 1 m9 VGND $end
$var supply1 1 n9 VPB $end
$var supply0 1 o9 VNB $end

$scope module base $end
$var wire 1 b9 X $end
$var wire 1 }& A0 $end
$var wire 1 a9 A1 $end
$var wire 1 d% S $end
$var wire 1 p9 mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_116 $end
$var wire 1 I$ Y $end
$var wire 1 f9 A $end
$var supply1 1 q9 VPWR $end
$var supply0 1 r9 VGND $end
$var supply1 1 s9 VPB $end
$var supply0 1 t9 VNB $end

$scope module base $end
$var wire 1 I$ Y $end
$var wire 1 f9 A $end
$var wire 1 u9 not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_117 $end
$var wire 1 f9 Y $end
$var wire 1 b9 A $end
$var supply1 1 v9 VPWR $end
$var supply0 1 w9 VGND $end
$var supply1 1 x9 VPB $end
$var supply0 1 y9 VNB $end

$scope module base $end
$var wire 1 f9 Y $end
$var wire 1 b9 A $end
$var wire 1 z9 not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_27 $end
$var wire 1 q# in [0] $end
$var wire 1 #$ in [1] $end
$var wire 1 e% sram [0] $end
$var wire 1 f% sram [1] $end
$var wire 1 ^' sram_inv [0] $end
$var wire 1 _' sram_inv [1] $end
$var wire 1 J$ out [0] $end
$var wire 1 1' p0 $end
$var wire 1 {9 mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 |9 mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 }9 SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 ~9 SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 !: SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 ": BUF_net_119 $end

$scope module mux_l1_in_0_ $end
$var wire 1 q# in [0] $end
$var wire 1 #$ in [1] $end
$var wire 1 e% mem [0] $end
$var wire 1 }9 mem_inv [0] $end
$var wire 1 {9 out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 {9 X $end
$var wire 1 #$ A0 $end
$var wire 1 q# A1 $end
$var wire 1 e% S $end
$var supply1 1 #: VPWR $end
$var supply0 1 $: VGND $end
$var supply1 1 %: VPB $end
$var supply0 1 &: VNB $end

$scope module base $end
$var wire 1 {9 X $end
$var wire 1 #$ A0 $end
$var wire 1 q# A1 $end
$var wire 1 e% S $end
$var wire 1 ': mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 {9 in [0] $end
$var wire 1 ~9 in [1] $end
$var wire 1 f% mem [0] $end
$var wire 1 !: mem_inv [0] $end
$var wire 1 |9 out [0] $end
$var wire 1 1' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 |9 X $end
$var wire 1 1' A0 $end
$var wire 1 {9 A1 $end
$var wire 1 f% S $end
$var supply1 1 (: VPWR $end
$var supply0 1 ): VGND $end
$var supply1 1 *: VPB $end
$var supply0 1 +: VNB $end

$scope module base $end
$var wire 1 |9 X $end
$var wire 1 1' A0 $end
$var wire 1 {9 A1 $end
$var wire 1 f% S $end
$var wire 1 ,: mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_118 $end
$var wire 1 J$ Y $end
$var wire 1 ": A $end
$var supply1 1 -: VPWR $end
$var supply0 1 .: VGND $end
$var supply1 1 /: VPB $end
$var supply0 1 0: VNB $end

$scope module base $end
$var wire 1 J$ Y $end
$var wire 1 ": A $end
$var wire 1 1: not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_119 $end
$var wire 1 ": Y $end
$var wire 1 |9 A $end
$var supply1 1 2: VPWR $end
$var supply0 1 3: VGND $end
$var supply1 1 4: VPB $end
$var supply0 1 5: VNB $end

$scope module base $end
$var wire 1 ": Y $end
$var wire 1 |9 A $end
$var wire 1 6: not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_39 $end
$var wire 1 k# in [0] $end
$var wire 1 )$ in [1] $end
$var wire 1 g% sram [0] $end
$var wire 1 h% sram [1] $end
$var wire 1 `' sram_inv [0] $end
$var wire 1 a' sram_inv [1] $end
$var wire 1 P$ out [0] $end
$var wire 1 Y' p0 $end
$var wire 1 7: mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 8: mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 9: SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 :: SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 ;: SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 <: BUF_net_121 $end

$scope module mux_l1_in_0_ $end
$var wire 1 k# in [0] $end
$var wire 1 )$ in [1] $end
$var wire 1 g% mem [0] $end
$var wire 1 9: mem_inv [0] $end
$var wire 1 7: out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 7: X $end
$var wire 1 )$ A0 $end
$var wire 1 k# A1 $end
$var wire 1 g% S $end
$var supply1 1 =: VPWR $end
$var supply0 1 >: VGND $end
$var supply1 1 ?: VPB $end
$var supply0 1 @: VNB $end

$scope module base $end
$var wire 1 7: X $end
$var wire 1 )$ A0 $end
$var wire 1 k# A1 $end
$var wire 1 g% S $end
$var wire 1 A: mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 7: in [0] $end
$var wire 1 :: in [1] $end
$var wire 1 h% mem [0] $end
$var wire 1 ;: mem_inv [0] $end
$var wire 1 8: out [0] $end
$var wire 1 Y' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 8: X $end
$var wire 1 Y' A0 $end
$var wire 1 7: A1 $end
$var wire 1 h% S $end
$var supply1 1 B: VPWR $end
$var supply0 1 C: VGND $end
$var supply1 1 D: VPB $end
$var supply0 1 E: VNB $end

$scope module base $end
$var wire 1 8: X $end
$var wire 1 Y' A0 $end
$var wire 1 7: A1 $end
$var wire 1 h% S $end
$var wire 1 F: mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_120 $end
$var wire 1 P$ Y $end
$var wire 1 <: A $end
$var supply1 1 G: VPWR $end
$var supply0 1 H: VGND $end
$var supply1 1 I: VPB $end
$var supply0 1 J: VNB $end

$scope module base $end
$var wire 1 P$ Y $end
$var wire 1 <: A $end
$var wire 1 K: not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_121 $end
$var wire 1 <: Y $end
$var wire 1 8: A $end
$var supply1 1 L: VPWR $end
$var supply0 1 M: VGND $end
$var supply1 1 N: VPB $end
$var supply0 1 O: VNB $end

$scope module base $end
$var wire 1 <: Y $end
$var wire 1 8: A $end
$var wire 1 P: not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_41 $end
$var wire 1 l# in [0] $end
$var wire 1 *$ in [1] $end
$var wire 1 i% sram [0] $end
$var wire 1 j% sram [1] $end
$var wire 1 b' sram_inv [0] $end
$var wire 1 c' sram_inv [1] $end
$var wire 1 Q$ out [0] $end
$var wire 1 R' p0 $end
$var wire 1 Q: mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 R: mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 S: SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 T: SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 U: SYNOPSYS_UNCONNECTED_3 $end

$scope module sky130_fd_sc_hd__buf_4_0_ $end
$var wire 1 Q$ X $end
$var wire 1 R: A $end
$var supply1 1 V: VPWR $end
$var supply0 1 W: VGND $end
$var supply1 1 X: VPB $end
$var supply0 1 Y: VNB $end

$scope module base $end
$var wire 1 Q$ X $end
$var wire 1 R: A $end
$var wire 1 Z: buf0_out_X $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 l# in [0] $end
$var wire 1 *$ in [1] $end
$var wire 1 i% mem [0] $end
$var wire 1 S: mem_inv [0] $end
$var wire 1 Q: out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 Q: X $end
$var wire 1 *$ A0 $end
$var wire 1 l# A1 $end
$var wire 1 i% S $end
$var supply1 1 [: VPWR $end
$var supply0 1 \: VGND $end
$var supply1 1 ]: VPB $end
$var supply0 1 ^: VNB $end

$scope module base $end
$var wire 1 Q: X $end
$var wire 1 *$ A0 $end
$var wire 1 l# A1 $end
$var wire 1 i% S $end
$var wire 1 _: mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 Q: in [0] $end
$var wire 1 T: in [1] $end
$var wire 1 j% mem [0] $end
$var wire 1 U: mem_inv [0] $end
$var wire 1 R: out [0] $end
$var wire 1 R' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 R: X $end
$var wire 1 R' A0 $end
$var wire 1 Q: A1 $end
$var wire 1 j% S $end
$var supply1 1 `: VPWR $end
$var supply0 1 a: VGND $end
$var supply1 1 b: VPB $end
$var supply0 1 c: VNB $end

$scope module base $end
$var wire 1 R: X $end
$var wire 1 R' A0 $end
$var wire 1 Q: A1 $end
$var wire 1 j% S $end
$var wire 1 d: mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_43 $end
$var wire 1 m# in [0] $end
$var wire 1 +$ in [1] $end
$var wire 1 #% sram [0] $end
$var wire 1 $% sram [1] $end
$var wire 1 d' sram_inv [0] $end
$var wire 1 e' sram_inv [1] $end
$var wire 1 R$ out [0] $end
$var wire 1 R' p0 $end
$var wire 1 e: mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 f: mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 g: SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 h: SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 i: SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 j: BUF_net_123 $end

$scope module mux_l1_in_0_ $end
$var wire 1 m# in [0] $end
$var wire 1 +$ in [1] $end
$var wire 1 #% mem [0] $end
$var wire 1 g: mem_inv [0] $end
$var wire 1 e: out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 e: X $end
$var wire 1 +$ A0 $end
$var wire 1 m# A1 $end
$var wire 1 #% S $end
$var supply1 1 k: VPWR $end
$var supply0 1 l: VGND $end
$var supply1 1 m: VPB $end
$var supply0 1 n: VNB $end

$scope module base $end
$var wire 1 e: X $end
$var wire 1 +$ A0 $end
$var wire 1 m# A1 $end
$var wire 1 #% S $end
$var wire 1 o: mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 e: in [0] $end
$var wire 1 h: in [1] $end
$var wire 1 $% mem [0] $end
$var wire 1 i: mem_inv [0] $end
$var wire 1 f: out [0] $end
$var wire 1 R' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 f: X $end
$var wire 1 R' A0 $end
$var wire 1 e: A1 $end
$var wire 1 $% S $end
$var supply1 1 p: VPWR $end
$var supply0 1 q: VGND $end
$var supply1 1 r: VPB $end
$var supply0 1 s: VNB $end

$scope module base $end
$var wire 1 f: X $end
$var wire 1 R' A0 $end
$var wire 1 e: A1 $end
$var wire 1 $% S $end
$var wire 1 t: mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_122 $end
$var wire 1 R$ Y $end
$var wire 1 j: A $end
$var supply1 1 u: VPWR $end
$var supply0 1 v: VGND $end
$var supply1 1 w: VPB $end
$var supply0 1 x: VNB $end

$scope module base $end
$var wire 1 R$ Y $end
$var wire 1 j: A $end
$var wire 1 y: not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_123 $end
$var wire 1 j: Y $end
$var wire 1 f: A $end
$var supply1 1 z: VPWR $end
$var supply0 1 {: VGND $end
$var supply1 1 |: VPB $end
$var supply0 1 }: VNB $end

$scope module base $end
$var wire 1 j: Y $end
$var wire 1 f: A $end
$var wire 1 ~: not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_47 $end
$var wire 1 o# in [0] $end
$var wire 1 -$ in [1] $end
$var wire 1 %% sram [0] $end
$var wire 1 &% sram [1] $end
$var wire 1 f' sram_inv [0] $end
$var wire 1 g' sram_inv [1] $end
$var wire 1 T$ out [0] $end
$var wire 1 R' p0 $end
$var wire 1 !; mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 "; mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 #; SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 $; SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 %; SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 &; BUF_net_125 $end

$scope module mux_l1_in_0_ $end
$var wire 1 o# in [0] $end
$var wire 1 -$ in [1] $end
$var wire 1 %% mem [0] $end
$var wire 1 #; mem_inv [0] $end
$var wire 1 !; out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 !; X $end
$var wire 1 -$ A0 $end
$var wire 1 o# A1 $end
$var wire 1 %% S $end
$var supply1 1 '; VPWR $end
$var supply0 1 (; VGND $end
$var supply1 1 ); VPB $end
$var supply0 1 *; VNB $end

$scope module base $end
$var wire 1 !; X $end
$var wire 1 -$ A0 $end
$var wire 1 o# A1 $end
$var wire 1 %% S $end
$var wire 1 +; mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 !; in [0] $end
$var wire 1 $; in [1] $end
$var wire 1 &% mem [0] $end
$var wire 1 %; mem_inv [0] $end
$var wire 1 "; out [0] $end
$var wire 1 R' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 "; X $end
$var wire 1 R' A0 $end
$var wire 1 !; A1 $end
$var wire 1 &% S $end
$var supply1 1 ,; VPWR $end
$var supply0 1 -; VGND $end
$var supply1 1 .; VPB $end
$var supply0 1 /; VNB $end

$scope module base $end
$var wire 1 "; X $end
$var wire 1 R' A0 $end
$var wire 1 !; A1 $end
$var wire 1 &% S $end
$var wire 1 0; mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_124 $end
$var wire 1 T$ Y $end
$var wire 1 &; A $end
$var supply1 1 1; VPWR $end
$var supply0 1 2; VGND $end
$var supply1 1 3; VPB $end
$var supply0 1 4; VNB $end

$scope module base $end
$var wire 1 T$ Y $end
$var wire 1 &; A $end
$var wire 1 5; not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_125 $end
$var wire 1 &; Y $end
$var wire 1 "; A $end
$var supply1 1 6; VPWR $end
$var supply0 1 7; VGND $end
$var supply1 1 8; VPB $end
$var supply0 1 9; VNB $end

$scope module base $end
$var wire 1 &; Y $end
$var wire 1 "; A $end
$var wire 1 :; not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_49 $end
$var wire 1 p# in [0] $end
$var wire 1 .$ in [1] $end
$var wire 1 '% sram [0] $end
$var wire 1 (% sram [1] $end
$var wire 1 h' sram_inv [0] $end
$var wire 1 i' sram_inv [1] $end
$var wire 1 U$ out [0] $end
$var wire 1 1' p0 $end
$var wire 1 ;; mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 <; mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 =; SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 >; SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 ?; SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 @; BUF_net_127 $end

$scope module mux_l1_in_0_ $end
$var wire 1 p# in [0] $end
$var wire 1 .$ in [1] $end
$var wire 1 '% mem [0] $end
$var wire 1 =; mem_inv [0] $end
$var wire 1 ;; out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 ;; X $end
$var wire 1 .$ A0 $end
$var wire 1 p# A1 $end
$var wire 1 '% S $end
$var supply1 1 A; VPWR $end
$var supply0 1 B; VGND $end
$var supply1 1 C; VPB $end
$var supply0 1 D; VNB $end

$scope module base $end
$var wire 1 ;; X $end
$var wire 1 .$ A0 $end
$var wire 1 p# A1 $end
$var wire 1 '% S $end
$var wire 1 E; mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 ;; in [0] $end
$var wire 1 >; in [1] $end
$var wire 1 (% mem [0] $end
$var wire 1 ?; mem_inv [0] $end
$var wire 1 <; out [0] $end
$var wire 1 1' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 <; X $end
$var wire 1 1' A0 $end
$var wire 1 ;; A1 $end
$var wire 1 (% S $end
$var supply1 1 F; VPWR $end
$var supply0 1 G; VGND $end
$var supply1 1 H; VPB $end
$var supply0 1 I; VNB $end

$scope module base $end
$var wire 1 <; X $end
$var wire 1 1' A0 $end
$var wire 1 ;; A1 $end
$var wire 1 (% S $end
$var wire 1 J; mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_126 $end
$var wire 1 U$ Y $end
$var wire 1 @; A $end
$var supply1 1 K; VPWR $end
$var supply0 1 L; VGND $end
$var supply1 1 M; VPB $end
$var supply0 1 N; VNB $end

$scope module base $end
$var wire 1 U$ Y $end
$var wire 1 @; A $end
$var wire 1 O; not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_127 $end
$var wire 1 @; Y $end
$var wire 1 <; A $end
$var supply1 1 P; VPWR $end
$var supply0 1 Q; VGND $end
$var supply1 1 R; VPB $end
$var supply0 1 S; VNB $end

$scope module base $end
$var wire 1 @; Y $end
$var wire 1 <; A $end
$var wire 1 T; not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_51 $end
$var wire 1 q# in [0] $end
$var wire 1 /$ in [1] $end
$var wire 1 )% sram [0] $end
$var wire 1 *% sram [1] $end
$var wire 1 j' sram_inv [0] $end
$var wire 1 k' sram_inv [1] $end
$var wire 1 V$ out [0] $end
$var wire 1 1' p0 $end
$var wire 1 U; mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 V; mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 W; SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 X; SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 Y; SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 Z; BUF_net_129 $end

$scope module mux_l1_in_0_ $end
$var wire 1 q# in [0] $end
$var wire 1 /$ in [1] $end
$var wire 1 )% mem [0] $end
$var wire 1 W; mem_inv [0] $end
$var wire 1 U; out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 U; X $end
$var wire 1 /$ A0 $end
$var wire 1 q# A1 $end
$var wire 1 )% S $end
$var supply1 1 [; VPWR $end
$var supply0 1 \; VGND $end
$var supply1 1 ]; VPB $end
$var supply0 1 ^; VNB $end

$scope module base $end
$var wire 1 U; X $end
$var wire 1 /$ A0 $end
$var wire 1 q# A1 $end
$var wire 1 )% S $end
$var wire 1 _; mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 U; in [0] $end
$var wire 1 X; in [1] $end
$var wire 1 *% mem [0] $end
$var wire 1 Y; mem_inv [0] $end
$var wire 1 V; out [0] $end
$var wire 1 1' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 V; X $end
$var wire 1 1' A0 $end
$var wire 1 U; A1 $end
$var wire 1 *% S $end
$var supply1 1 `; VPWR $end
$var supply0 1 a; VGND $end
$var supply1 1 b; VPB $end
$var supply0 1 c; VNB $end

$scope module base $end
$var wire 1 V; X $end
$var wire 1 1' A0 $end
$var wire 1 U; A1 $end
$var wire 1 *% S $end
$var wire 1 d; mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_128 $end
$var wire 1 V$ Y $end
$var wire 1 Z; A $end
$var supply1 1 e; VPWR $end
$var supply0 1 f; VGND $end
$var supply1 1 g; VPB $end
$var supply0 1 h; VNB $end

$scope module base $end
$var wire 1 V$ Y $end
$var wire 1 Z; A $end
$var wire 1 i; not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_129 $end
$var wire 1 Z; Y $end
$var wire 1 V; A $end
$var supply1 1 j; VPWR $end
$var supply0 1 k; VGND $end
$var supply1 1 l; VPB $end
$var supply0 1 m; VNB $end

$scope module base $end
$var wire 1 Z; Y $end
$var wire 1 V; A $end
$var wire 1 n; not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_53 $end
$var wire 1 r# in [0] $end
$var wire 1 0$ in [1] $end
$var wire 1 +% sram [0] $end
$var wire 1 ,% sram [1] $end
$var wire 1 l' sram_inv [0] $end
$var wire 1 m' sram_inv [1] $end
$var wire 1 W$ out [0] $end
$var wire 1 (' p0 $end
$var wire 1 o; mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 p; mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 q; SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 r; SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 s; SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 t; BUF_net_131 $end

$scope module mux_l1_in_0_ $end
$var wire 1 r# in [0] $end
$var wire 1 0$ in [1] $end
$var wire 1 +% mem [0] $end
$var wire 1 q; mem_inv [0] $end
$var wire 1 o; out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 o; X $end
$var wire 1 0$ A0 $end
$var wire 1 r# A1 $end
$var wire 1 +% S $end
$var supply1 1 u; VPWR $end
$var supply0 1 v; VGND $end
$var supply1 1 w; VPB $end
$var supply0 1 x; VNB $end

$scope module base $end
$var wire 1 o; X $end
$var wire 1 0$ A0 $end
$var wire 1 r# A1 $end
$var wire 1 +% S $end
$var wire 1 y; mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 o; in [0] $end
$var wire 1 r; in [1] $end
$var wire 1 ,% mem [0] $end
$var wire 1 s; mem_inv [0] $end
$var wire 1 p; out [0] $end
$var wire 1 (' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 p; X $end
$var wire 1 (' A0 $end
$var wire 1 o; A1 $end
$var wire 1 ,% S $end
$var supply1 1 z; VPWR $end
$var supply0 1 {; VGND $end
$var supply1 1 |; VPB $end
$var supply0 1 }; VNB $end

$scope module base $end
$var wire 1 p; X $end
$var wire 1 (' A0 $end
$var wire 1 o; A1 $end
$var wire 1 ,% S $end
$var wire 1 ~; mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_130 $end
$var wire 1 W$ Y $end
$var wire 1 t; A $end
$var supply1 1 !< VPWR $end
$var supply0 1 "< VGND $end
$var supply1 1 #< VPB $end
$var supply0 1 $< VNB $end

$scope module base $end
$var wire 1 W$ Y $end
$var wire 1 t; A $end
$var wire 1 %< not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_131 $end
$var wire 1 t; Y $end
$var wire 1 p; A $end
$var supply1 1 &< VPWR $end
$var supply0 1 '< VGND $end
$var supply1 1 (< VPB $end
$var supply0 1 )< VNB $end

$scope module base $end
$var wire 1 t; Y $end
$var wire 1 p; A $end
$var wire 1 *< not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_13 $end
$var wire 1 Q# in [0] $end
$var wire 1 3$ in [1] $end
$var wire 1 -% sram [0] $end
$var wire 1 .% sram [1] $end
$var wire 1 n' sram_inv [0] $end
$var wire 1 o' sram_inv [1] $end
$var wire 1 a$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 +< mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 ,< mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 -< SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 .< SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 /< SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 0< BUF_net_133 $end

$scope module mux_l1_in_0_ $end
$var wire 1 Q# in [0] $end
$var wire 1 3$ in [1] $end
$var wire 1 -% mem [0] $end
$var wire 1 -< mem_inv [0] $end
$var wire 1 +< out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 +< X $end
$var wire 1 3$ A0 $end
$var wire 1 Q# A1 $end
$var wire 1 -% S $end
$var supply1 1 1< VPWR $end
$var supply0 1 2< VGND $end
$var supply1 1 3< VPB $end
$var supply0 1 4< VNB $end

$scope module base $end
$var wire 1 +< X $end
$var wire 1 3$ A0 $end
$var wire 1 Q# A1 $end
$var wire 1 -% S $end
$var wire 1 5< mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 +< in [0] $end
$var wire 1 .< in [1] $end
$var wire 1 .% mem [0] $end
$var wire 1 /< mem_inv [0] $end
$var wire 1 ,< out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 ,< X $end
$var wire 1 p' A0 $end
$var wire 1 +< A1 $end
$var wire 1 .% S $end
$var supply1 1 6< VPWR $end
$var supply0 1 7< VGND $end
$var supply1 1 8< VPB $end
$var supply0 1 9< VNB $end

$scope module base $end
$var wire 1 ,< X $end
$var wire 1 p' A0 $end
$var wire 1 +< A1 $end
$var wire 1 .% S $end
$var wire 1 :< mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_132 $end
$var wire 1 a$ Y $end
$var wire 1 0< A $end
$var supply1 1 ;< VPWR $end
$var supply0 1 << VGND $end
$var supply1 1 =< VPB $end
$var supply0 1 >< VNB $end

$scope module base $end
$var wire 1 a$ Y $end
$var wire 1 0< A $end
$var wire 1 ?< not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_133 $end
$var wire 1 0< Y $end
$var wire 1 ,< A $end
$var supply1 1 @< VPWR $end
$var supply0 1 A< VGND $end
$var supply1 1 B< VPB $end
$var supply0 1 C< VNB $end

$scope module base $end
$var wire 1 0< Y $end
$var wire 1 ,< A $end
$var wire 1 D< not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_15 $end
$var wire 1 R# in [0] $end
$var wire 1 4$ in [1] $end
$var wire 1 /% sram [0] $end
$var wire 1 0% sram [1] $end
$var wire 1 q' sram_inv [0] $end
$var wire 1 r' sram_inv [1] $end
$var wire 1 b$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 E< mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 F< mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 G< SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 H< SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 I< SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 J< BUF_net_135 $end

$scope module mux_l1_in_0_ $end
$var wire 1 R# in [0] $end
$var wire 1 4$ in [1] $end
$var wire 1 /% mem [0] $end
$var wire 1 G< mem_inv [0] $end
$var wire 1 E< out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 E< X $end
$var wire 1 4$ A0 $end
$var wire 1 R# A1 $end
$var wire 1 /% S $end
$var supply1 1 K< VPWR $end
$var supply0 1 L< VGND $end
$var supply1 1 M< VPB $end
$var supply0 1 N< VNB $end

$scope module base $end
$var wire 1 E< X $end
$var wire 1 4$ A0 $end
$var wire 1 R# A1 $end
$var wire 1 /% S $end
$var wire 1 O< mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 E< in [0] $end
$var wire 1 H< in [1] $end
$var wire 1 0% mem [0] $end
$var wire 1 I< mem_inv [0] $end
$var wire 1 F< out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 F< X $end
$var wire 1 p' A0 $end
$var wire 1 E< A1 $end
$var wire 1 0% S $end
$var supply1 1 P< VPWR $end
$var supply0 1 Q< VGND $end
$var supply1 1 R< VPB $end
$var supply0 1 S< VNB $end

$scope module base $end
$var wire 1 F< X $end
$var wire 1 p' A0 $end
$var wire 1 E< A1 $end
$var wire 1 0% S $end
$var wire 1 T< mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_134 $end
$var wire 1 b$ Y $end
$var wire 1 J< A $end
$var supply1 1 U< VPWR $end
$var supply0 1 V< VGND $end
$var supply1 1 W< VPB $end
$var supply0 1 X< VNB $end

$scope module base $end
$var wire 1 b$ Y $end
$var wire 1 J< A $end
$var wire 1 Y< not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_135 $end
$var wire 1 J< Y $end
$var wire 1 F< A $end
$var supply1 1 Z< VPWR $end
$var supply0 1 [< VGND $end
$var supply1 1 \< VPB $end
$var supply0 1 ]< VNB $end

$scope module base $end
$var wire 1 J< Y $end
$var wire 1 F< A $end
$var wire 1 ^< not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_17 $end
$var wire 1 S# in [0] $end
$var wire 1 5$ in [1] $end
$var wire 1 1% sram [0] $end
$var wire 1 2% sram [1] $end
$var wire 1 s' sram_inv [0] $end
$var wire 1 t' sram_inv [1] $end
$var wire 1 c$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 _< mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 `< mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 a< SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 b< SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 c< SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 d< BUF_net_137 $end

$scope module mux_l1_in_0_ $end
$var wire 1 S# in [0] $end
$var wire 1 5$ in [1] $end
$var wire 1 1% mem [0] $end
$var wire 1 a< mem_inv [0] $end
$var wire 1 _< out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 _< X $end
$var wire 1 5$ A0 $end
$var wire 1 S# A1 $end
$var wire 1 1% S $end
$var supply1 1 e< VPWR $end
$var supply0 1 f< VGND $end
$var supply1 1 g< VPB $end
$var supply0 1 h< VNB $end

$scope module base $end
$var wire 1 _< X $end
$var wire 1 5$ A0 $end
$var wire 1 S# A1 $end
$var wire 1 1% S $end
$var wire 1 i< mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 _< in [0] $end
$var wire 1 b< in [1] $end
$var wire 1 2% mem [0] $end
$var wire 1 c< mem_inv [0] $end
$var wire 1 `< out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 `< X $end
$var wire 1 p' A0 $end
$var wire 1 _< A1 $end
$var wire 1 2% S $end
$var supply1 1 j< VPWR $end
$var supply0 1 k< VGND $end
$var supply1 1 l< VPB $end
$var supply0 1 m< VNB $end

$scope module base $end
$var wire 1 `< X $end
$var wire 1 p' A0 $end
$var wire 1 _< A1 $end
$var wire 1 2% S $end
$var wire 1 n< mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_136 $end
$var wire 1 c$ Y $end
$var wire 1 d< A $end
$var supply1 1 o< VPWR $end
$var supply0 1 p< VGND $end
$var supply1 1 q< VPB $end
$var supply0 1 r< VNB $end

$scope module base $end
$var wire 1 c$ Y $end
$var wire 1 d< A $end
$var wire 1 s< not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_137 $end
$var wire 1 d< Y $end
$var wire 1 `< A $end
$var supply1 1 t< VPWR $end
$var supply0 1 u< VGND $end
$var supply1 1 v< VPB $end
$var supply0 1 w< VNB $end

$scope module base $end
$var wire 1 d< Y $end
$var wire 1 `< A $end
$var wire 1 x< not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_19 $end
$var wire 1 T# in [0] $end
$var wire 1 6$ in [1] $end
$var wire 1 3% sram [0] $end
$var wire 1 4% sram [1] $end
$var wire 1 u' sram_inv [0] $end
$var wire 1 v' sram_inv [1] $end
$var wire 1 d$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 y< mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 z< mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 {< SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 |< SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 }< SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 ~< BUF_net_139 $end

$scope module mux_l1_in_0_ $end
$var wire 1 T# in [0] $end
$var wire 1 6$ in [1] $end
$var wire 1 3% mem [0] $end
$var wire 1 {< mem_inv [0] $end
$var wire 1 y< out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 y< X $end
$var wire 1 6$ A0 $end
$var wire 1 T# A1 $end
$var wire 1 3% S $end
$var supply1 1 != VPWR $end
$var supply0 1 "= VGND $end
$var supply1 1 #= VPB $end
$var supply0 1 $= VNB $end

$scope module base $end
$var wire 1 y< X $end
$var wire 1 6$ A0 $end
$var wire 1 T# A1 $end
$var wire 1 3% S $end
$var wire 1 %= mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 y< in [0] $end
$var wire 1 |< in [1] $end
$var wire 1 4% mem [0] $end
$var wire 1 }< mem_inv [0] $end
$var wire 1 z< out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 z< X $end
$var wire 1 p' A0 $end
$var wire 1 y< A1 $end
$var wire 1 4% S $end
$var supply1 1 &= VPWR $end
$var supply0 1 '= VGND $end
$var supply1 1 (= VPB $end
$var supply0 1 )= VNB $end

$scope module base $end
$var wire 1 z< X $end
$var wire 1 p' A0 $end
$var wire 1 y< A1 $end
$var wire 1 4% S $end
$var wire 1 *= mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_138 $end
$var wire 1 d$ Y $end
$var wire 1 ~< A $end
$var supply1 1 += VPWR $end
$var supply0 1 ,= VGND $end
$var supply1 1 -= VPB $end
$var supply0 1 .= VNB $end

$scope module base $end
$var wire 1 d$ Y $end
$var wire 1 ~< A $end
$var wire 1 /= not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_139 $end
$var wire 1 ~< Y $end
$var wire 1 z< A $end
$var supply1 1 0= VPWR $end
$var supply0 1 1= VGND $end
$var supply1 1 2= VPB $end
$var supply0 1 3= VNB $end

$scope module base $end
$var wire 1 ~< Y $end
$var wire 1 z< A $end
$var wire 1 4= not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_21 $end
$var wire 1 U# in [0] $end
$var wire 1 7$ in [1] $end
$var wire 1 5% sram [0] $end
$var wire 1 6% sram [1] $end
$var wire 1 w' sram_inv [0] $end
$var wire 1 x' sram_inv [1] $end
$var wire 1 e$ out [0] $end
$var wire 1 R' p0 $end
$var wire 1 5= mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 6= mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 7= SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 8= SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 9= SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 := BUF_net_141 $end

$scope module mux_l1_in_0_ $end
$var wire 1 U# in [0] $end
$var wire 1 7$ in [1] $end
$var wire 1 5% mem [0] $end
$var wire 1 7= mem_inv [0] $end
$var wire 1 5= out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 5= X $end
$var wire 1 7$ A0 $end
$var wire 1 U# A1 $end
$var wire 1 5% S $end
$var supply1 1 ;= VPWR $end
$var supply0 1 <= VGND $end
$var supply1 1 == VPB $end
$var supply0 1 >= VNB $end

$scope module base $end
$var wire 1 5= X $end
$var wire 1 7$ A0 $end
$var wire 1 U# A1 $end
$var wire 1 5% S $end
$var wire 1 ?= mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 5= in [0] $end
$var wire 1 8= in [1] $end
$var wire 1 6% mem [0] $end
$var wire 1 9= mem_inv [0] $end
$var wire 1 6= out [0] $end
$var wire 1 R' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 6= X $end
$var wire 1 R' A0 $end
$var wire 1 5= A1 $end
$var wire 1 6% S $end
$var supply1 1 @= VPWR $end
$var supply0 1 A= VGND $end
$var supply1 1 B= VPB $end
$var supply0 1 C= VNB $end

$scope module base $end
$var wire 1 6= X $end
$var wire 1 R' A0 $end
$var wire 1 5= A1 $end
$var wire 1 6% S $end
$var wire 1 D= mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_140 $end
$var wire 1 e$ Y $end
$var wire 1 := A $end
$var supply1 1 E= VPWR $end
$var supply0 1 F= VGND $end
$var supply1 1 G= VPB $end
$var supply0 1 H= VNB $end

$scope module base $end
$var wire 1 e$ Y $end
$var wire 1 := A $end
$var wire 1 I= not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_141 $end
$var wire 1 := Y $end
$var wire 1 6= A $end
$var supply1 1 J= VPWR $end
$var supply0 1 K= VGND $end
$var supply1 1 L= VPB $end
$var supply0 1 M= VNB $end

$scope module base $end
$var wire 1 := Y $end
$var wire 1 6= A $end
$var wire 1 N= not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_23 $end
$var wire 1 V# in [0] $end
$var wire 1 8$ in [1] $end
$var wire 1 9% sram [0] $end
$var wire 1 :% sram [1] $end
$var wire 1 y' sram_inv [0] $end
$var wire 1 z' sram_inv [1] $end
$var wire 1 f$ out [0] $end
$var wire 1 R' p0 $end
$var wire 1 O= mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 P= mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 Q= SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 R= SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 S= SYNOPSYS_UNCONNECTED_3 $end

$scope module sky130_fd_sc_hd__buf_4_0_ $end
$var wire 1 f$ X $end
$var wire 1 P= A $end
$var supply1 1 T= VPWR $end
$var supply0 1 U= VGND $end
$var supply1 1 V= VPB $end
$var supply0 1 W= VNB $end

$scope module base $end
$var wire 1 f$ X $end
$var wire 1 P= A $end
$var wire 1 X= buf0_out_X $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 V# in [0] $end
$var wire 1 8$ in [1] $end
$var wire 1 9% mem [0] $end
$var wire 1 Q= mem_inv [0] $end
$var wire 1 O= out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 O= X $end
$var wire 1 8$ A0 $end
$var wire 1 V# A1 $end
$var wire 1 9% S $end
$var supply1 1 Y= VPWR $end
$var supply0 1 Z= VGND $end
$var supply1 1 [= VPB $end
$var supply0 1 \= VNB $end

$scope module base $end
$var wire 1 O= X $end
$var wire 1 8$ A0 $end
$var wire 1 V# A1 $end
$var wire 1 9% S $end
$var wire 1 ]= mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 O= in [0] $end
$var wire 1 R= in [1] $end
$var wire 1 :% mem [0] $end
$var wire 1 S= mem_inv [0] $end
$var wire 1 P= out [0] $end
$var wire 1 R' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 P= X $end
$var wire 1 R' A0 $end
$var wire 1 O= A1 $end
$var wire 1 :% S $end
$var supply1 1 ^= VPWR $end
$var supply0 1 _= VGND $end
$var supply1 1 `= VPB $end
$var supply0 1 a= VNB $end

$scope module base $end
$var wire 1 P= X $end
$var wire 1 R' A0 $end
$var wire 1 O= A1 $end
$var wire 1 :% S $end
$var wire 1 b= mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_25 $end
$var wire 1 W# in [0] $end
$var wire 1 9$ in [1] $end
$var wire 1 ;% sram [0] $end
$var wire 1 <% sram [1] $end
$var wire 1 {' sram_inv [0] $end
$var wire 1 |' sram_inv [1] $end
$var wire 1 g$ out [0] $end
$var wire 1 R' p0 $end
$var wire 1 c= mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 d= mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 e= SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 f= SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 g= SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 h= BUF_net_143 $end

$scope module mux_l1_in_0_ $end
$var wire 1 W# in [0] $end
$var wire 1 9$ in [1] $end
$var wire 1 ;% mem [0] $end
$var wire 1 e= mem_inv [0] $end
$var wire 1 c= out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 c= X $end
$var wire 1 9$ A0 $end
$var wire 1 W# A1 $end
$var wire 1 ;% S $end
$var supply1 1 i= VPWR $end
$var supply0 1 j= VGND $end
$var supply1 1 k= VPB $end
$var supply0 1 l= VNB $end

$scope module base $end
$var wire 1 c= X $end
$var wire 1 9$ A0 $end
$var wire 1 W# A1 $end
$var wire 1 ;% S $end
$var wire 1 m= mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 c= in [0] $end
$var wire 1 f= in [1] $end
$var wire 1 <% mem [0] $end
$var wire 1 g= mem_inv [0] $end
$var wire 1 d= out [0] $end
$var wire 1 R' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 d= X $end
$var wire 1 R' A0 $end
$var wire 1 c= A1 $end
$var wire 1 <% S $end
$var supply1 1 n= VPWR $end
$var supply0 1 o= VGND $end
$var supply1 1 p= VPB $end
$var supply0 1 q= VNB $end

$scope module base $end
$var wire 1 d= X $end
$var wire 1 R' A0 $end
$var wire 1 c= A1 $end
$var wire 1 <% S $end
$var wire 1 r= mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_142 $end
$var wire 1 g$ Y $end
$var wire 1 h= A $end
$var supply1 1 s= VPWR $end
$var supply0 1 t= VGND $end
$var supply1 1 u= VPB $end
$var supply0 1 v= VNB $end

$scope module base $end
$var wire 1 g$ Y $end
$var wire 1 h= A $end
$var wire 1 w= not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_143 $end
$var wire 1 h= Y $end
$var wire 1 d= A $end
$var supply1 1 x= VPWR $end
$var supply0 1 y= VGND $end
$var supply1 1 z= VPB $end
$var supply0 1 {= VNB $end

$scope module base $end
$var wire 1 h= Y $end
$var wire 1 d= A $end
$var wire 1 |= not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_27 $end
$var wire 1 X# in [0] $end
$var wire 1 :$ in [1] $end
$var wire 1 =% sram [0] $end
$var wire 1 >% sram [1] $end
$var wire 1 }' sram_inv [0] $end
$var wire 1 ~' sram_inv [1] $end
$var wire 1 h$ out [0] $end
$var wire 1 R' p0 $end
$var wire 1 }= mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 ~= mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 !> SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 "> SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 #> SYNOPSYS_UNCONNECTED_3 $end

$scope module sky130_fd_sc_hd__buf_4_0_ $end
$var wire 1 h$ X $end
$var wire 1 ~= A $end
$var supply1 1 $> VPWR $end
$var supply0 1 %> VGND $end
$var supply1 1 &> VPB $end
$var supply0 1 '> VNB $end

$scope module base $end
$var wire 1 h$ X $end
$var wire 1 ~= A $end
$var wire 1 (> buf0_out_X $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 X# in [0] $end
$var wire 1 :$ in [1] $end
$var wire 1 =% mem [0] $end
$var wire 1 !> mem_inv [0] $end
$var wire 1 }= out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 }= X $end
$var wire 1 :$ A0 $end
$var wire 1 X# A1 $end
$var wire 1 =% S $end
$var supply1 1 )> VPWR $end
$var supply0 1 *> VGND $end
$var supply1 1 +> VPB $end
$var supply0 1 ,> VNB $end

$scope module base $end
$var wire 1 }= X $end
$var wire 1 :$ A0 $end
$var wire 1 X# A1 $end
$var wire 1 =% S $end
$var wire 1 -> mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 }= in [0] $end
$var wire 1 "> in [1] $end
$var wire 1 >% mem [0] $end
$var wire 1 #> mem_inv [0] $end
$var wire 1 ~= out [0] $end
$var wire 1 R' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 ~= X $end
$var wire 1 R' A0 $end
$var wire 1 }= A1 $end
$var wire 1 >% S $end
$var supply1 1 .> VPWR $end
$var supply0 1 /> VGND $end
$var supply1 1 0> VPB $end
$var supply0 1 1> VNB $end

$scope module base $end
$var wire 1 ~= X $end
$var wire 1 R' A0 $end
$var wire 1 }= A1 $end
$var wire 1 >% S $end
$var wire 1 2> mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_31 $end
$var wire 1 Z# in [0] $end
$var wire 1 4$ in [1] $end
$var wire 1 ?% sram [0] $end
$var wire 1 @% sram [1] $end
$var wire 1 !( sram_inv [0] $end
$var wire 1 "( sram_inv [1] $end
$var wire 1 j$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 3> mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 4> mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 5> SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 6> SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 7> SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 8> BUF_net_145 $end

$scope module mux_l1_in_0_ $end
$var wire 1 Z# in [0] $end
$var wire 1 4$ in [1] $end
$var wire 1 ?% mem [0] $end
$var wire 1 5> mem_inv [0] $end
$var wire 1 3> out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 3> X $end
$var wire 1 4$ A0 $end
$var wire 1 Z# A1 $end
$var wire 1 ?% S $end
$var supply1 1 9> VPWR $end
$var supply0 1 :> VGND $end
$var supply1 1 ;> VPB $end
$var supply0 1 <> VNB $end

$scope module base $end
$var wire 1 3> X $end
$var wire 1 4$ A0 $end
$var wire 1 Z# A1 $end
$var wire 1 ?% S $end
$var wire 1 => mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 3> in [0] $end
$var wire 1 6> in [1] $end
$var wire 1 @% mem [0] $end
$var wire 1 7> mem_inv [0] $end
$var wire 1 4> out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 4> X $end
$var wire 1 p' A0 $end
$var wire 1 3> A1 $end
$var wire 1 @% S $end
$var supply1 1 >> VPWR $end
$var supply0 1 ?> VGND $end
$var supply1 1 @> VPB $end
$var supply0 1 A> VNB $end

$scope module base $end
$var wire 1 4> X $end
$var wire 1 p' A0 $end
$var wire 1 3> A1 $end
$var wire 1 @% S $end
$var wire 1 B> mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_144 $end
$var wire 1 j$ Y $end
$var wire 1 8> A $end
$var supply1 1 C> VPWR $end
$var supply0 1 D> VGND $end
$var supply1 1 E> VPB $end
$var supply0 1 F> VNB $end

$scope module base $end
$var wire 1 j$ Y $end
$var wire 1 8> A $end
$var wire 1 G> not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_145 $end
$var wire 1 8> Y $end
$var wire 1 4> A $end
$var supply1 1 H> VPWR $end
$var supply0 1 I> VGND $end
$var supply1 1 J> VPB $end
$var supply0 1 K> VNB $end

$scope module base $end
$var wire 1 8> Y $end
$var wire 1 4> A $end
$var wire 1 L> not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_33 $end
$var wire 1 [# in [0] $end
$var wire 1 5$ in [1] $end
$var wire 1 A% sram [0] $end
$var wire 1 B% sram [1] $end
$var wire 1 #( sram_inv [0] $end
$var wire 1 $( sram_inv [1] $end
$var wire 1 k$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 M> mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 N> mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 O> SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 P> SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 Q> SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 R> BUF_net_147 $end

$scope module mux_l1_in_0_ $end
$var wire 1 [# in [0] $end
$var wire 1 5$ in [1] $end
$var wire 1 A% mem [0] $end
$var wire 1 O> mem_inv [0] $end
$var wire 1 M> out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 M> X $end
$var wire 1 5$ A0 $end
$var wire 1 [# A1 $end
$var wire 1 A% S $end
$var supply1 1 S> VPWR $end
$var supply0 1 T> VGND $end
$var supply1 1 U> VPB $end
$var supply0 1 V> VNB $end

$scope module base $end
$var wire 1 M> X $end
$var wire 1 5$ A0 $end
$var wire 1 [# A1 $end
$var wire 1 A% S $end
$var wire 1 W> mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 M> in [0] $end
$var wire 1 P> in [1] $end
$var wire 1 B% mem [0] $end
$var wire 1 Q> mem_inv [0] $end
$var wire 1 N> out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 N> X $end
$var wire 1 p' A0 $end
$var wire 1 M> A1 $end
$var wire 1 B% S $end
$var supply1 1 X> VPWR $end
$var supply0 1 Y> VGND $end
$var supply1 1 Z> VPB $end
$var supply0 1 [> VNB $end

$scope module base $end
$var wire 1 N> X $end
$var wire 1 p' A0 $end
$var wire 1 M> A1 $end
$var wire 1 B% S $end
$var wire 1 \> mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_146 $end
$var wire 1 k$ Y $end
$var wire 1 R> A $end
$var supply1 1 ]> VPWR $end
$var supply0 1 ^> VGND $end
$var supply1 1 _> VPB $end
$var supply0 1 `> VNB $end

$scope module base $end
$var wire 1 k$ Y $end
$var wire 1 R> A $end
$var wire 1 a> not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_147 $end
$var wire 1 R> Y $end
$var wire 1 N> A $end
$var supply1 1 b> VPWR $end
$var supply0 1 c> VGND $end
$var supply1 1 d> VPB $end
$var supply0 1 e> VNB $end

$scope module base $end
$var wire 1 R> Y $end
$var wire 1 N> A $end
$var wire 1 f> not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_35 $end
$var wire 1 \# in [0] $end
$var wire 1 6$ in [1] $end
$var wire 1 C% sram [0] $end
$var wire 1 D% sram [1] $end
$var wire 1 %( sram_inv [0] $end
$var wire 1 &( sram_inv [1] $end
$var wire 1 l$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 g> mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 h> mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 i> SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 j> SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 k> SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 l> BUF_net_149 $end

$scope module mux_l1_in_0_ $end
$var wire 1 \# in [0] $end
$var wire 1 6$ in [1] $end
$var wire 1 C% mem [0] $end
$var wire 1 i> mem_inv [0] $end
$var wire 1 g> out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 g> X $end
$var wire 1 6$ A0 $end
$var wire 1 \# A1 $end
$var wire 1 C% S $end
$var supply1 1 m> VPWR $end
$var supply0 1 n> VGND $end
$var supply1 1 o> VPB $end
$var supply0 1 p> VNB $end

$scope module base $end
$var wire 1 g> X $end
$var wire 1 6$ A0 $end
$var wire 1 \# A1 $end
$var wire 1 C% S $end
$var wire 1 q> mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 g> in [0] $end
$var wire 1 j> in [1] $end
$var wire 1 D% mem [0] $end
$var wire 1 k> mem_inv [0] $end
$var wire 1 h> out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 h> X $end
$var wire 1 p' A0 $end
$var wire 1 g> A1 $end
$var wire 1 D% S $end
$var supply1 1 r> VPWR $end
$var supply0 1 s> VGND $end
$var supply1 1 t> VPB $end
$var supply0 1 u> VNB $end

$scope module base $end
$var wire 1 h> X $end
$var wire 1 p' A0 $end
$var wire 1 g> A1 $end
$var wire 1 D% S $end
$var wire 1 v> mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_148 $end
$var wire 1 l$ Y $end
$var wire 1 l> A $end
$var supply1 1 w> VPWR $end
$var supply0 1 x> VGND $end
$var supply1 1 y> VPB $end
$var supply0 1 z> VNB $end

$scope module base $end
$var wire 1 l$ Y $end
$var wire 1 l> A $end
$var wire 1 {> not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_149 $end
$var wire 1 l> Y $end
$var wire 1 h> A $end
$var supply1 1 |> VPWR $end
$var supply0 1 }> VGND $end
$var supply1 1 ~> VPB $end
$var supply0 1 !? VNB $end

$scope module base $end
$var wire 1 l> Y $end
$var wire 1 h> A $end
$var wire 1 "? not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_37 $end
$var wire 1 ]# in [0] $end
$var wire 1 7$ in [1] $end
$var wire 1 E% sram [0] $end
$var wire 1 F% sram [1] $end
$var wire 1 '( sram_inv [0] $end
$var wire 1 (( sram_inv [1] $end
$var wire 1 m$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 #? mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 $? mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 %? SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 &? SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 '? SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 (? BUF_net_151 $end

$scope module mux_l1_in_0_ $end
$var wire 1 ]# in [0] $end
$var wire 1 7$ in [1] $end
$var wire 1 E% mem [0] $end
$var wire 1 %? mem_inv [0] $end
$var wire 1 #? out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 #? X $end
$var wire 1 7$ A0 $end
$var wire 1 ]# A1 $end
$var wire 1 E% S $end
$var supply1 1 )? VPWR $end
$var supply0 1 *? VGND $end
$var supply1 1 +? VPB $end
$var supply0 1 ,? VNB $end

$scope module base $end
$var wire 1 #? X $end
$var wire 1 7$ A0 $end
$var wire 1 ]# A1 $end
$var wire 1 E% S $end
$var wire 1 -? mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 #? in [0] $end
$var wire 1 &? in [1] $end
$var wire 1 F% mem [0] $end
$var wire 1 '? mem_inv [0] $end
$var wire 1 $? out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 $? X $end
$var wire 1 p' A0 $end
$var wire 1 #? A1 $end
$var wire 1 F% S $end
$var supply1 1 .? VPWR $end
$var supply0 1 /? VGND $end
$var supply1 1 0? VPB $end
$var supply0 1 1? VNB $end

$scope module base $end
$var wire 1 $? X $end
$var wire 1 p' A0 $end
$var wire 1 #? A1 $end
$var wire 1 F% S $end
$var wire 1 2? mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_150 $end
$var wire 1 m$ Y $end
$var wire 1 (? A $end
$var supply1 1 3? VPWR $end
$var supply0 1 4? VGND $end
$var supply1 1 5? VPB $end
$var supply0 1 6? VNB $end

$scope module base $end
$var wire 1 m$ Y $end
$var wire 1 (? A $end
$var wire 1 7? not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_151 $end
$var wire 1 (? Y $end
$var wire 1 $? A $end
$var supply1 1 8? VPWR $end
$var supply0 1 9? VGND $end
$var supply1 1 :? VPB $end
$var supply0 1 ;? VNB $end

$scope module base $end
$var wire 1 (? Y $end
$var wire 1 $? A $end
$var wire 1 <? not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_39 $end
$var wire 1 ^# in [0] $end
$var wire 1 8$ in [1] $end
$var wire 1 G% sram [0] $end
$var wire 1 H% sram [1] $end
$var wire 1 )( sram_inv [0] $end
$var wire 1 *( sram_inv [1] $end
$var wire 1 n$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 =? mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 >? mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 ?? SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 @? SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 A? SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 B? BUF_net_153 $end

$scope module mux_l1_in_0_ $end
$var wire 1 ^# in [0] $end
$var wire 1 8$ in [1] $end
$var wire 1 G% mem [0] $end
$var wire 1 ?? mem_inv [0] $end
$var wire 1 =? out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 =? X $end
$var wire 1 8$ A0 $end
$var wire 1 ^# A1 $end
$var wire 1 G% S $end
$var supply1 1 C? VPWR $end
$var supply0 1 D? VGND $end
$var supply1 1 E? VPB $end
$var supply0 1 F? VNB $end

$scope module base $end
$var wire 1 =? X $end
$var wire 1 8$ A0 $end
$var wire 1 ^# A1 $end
$var wire 1 G% S $end
$var wire 1 G? mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 =? in [0] $end
$var wire 1 @? in [1] $end
$var wire 1 H% mem [0] $end
$var wire 1 A? mem_inv [0] $end
$var wire 1 >? out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 >? X $end
$var wire 1 p' A0 $end
$var wire 1 =? A1 $end
$var wire 1 H% S $end
$var supply1 1 H? VPWR $end
$var supply0 1 I? VGND $end
$var supply1 1 J? VPB $end
$var supply0 1 K? VNB $end

$scope module base $end
$var wire 1 >? X $end
$var wire 1 p' A0 $end
$var wire 1 =? A1 $end
$var wire 1 H% S $end
$var wire 1 L? mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_152 $end
$var wire 1 n$ Y $end
$var wire 1 B? A $end
$var supply1 1 M? VPWR $end
$var supply0 1 N? VGND $end
$var supply1 1 O? VPB $end
$var supply0 1 P? VNB $end

$scope module base $end
$var wire 1 n$ Y $end
$var wire 1 B? A $end
$var wire 1 Q? not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_153 $end
$var wire 1 B? Y $end
$var wire 1 >? A $end
$var supply1 1 R? VPWR $end
$var supply0 1 S? VGND $end
$var supply1 1 T? VPB $end
$var supply0 1 U? VNB $end

$scope module base $end
$var wire 1 B? Y $end
$var wire 1 >? A $end
$var wire 1 V? not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_41 $end
$var wire 1 _# in [0] $end
$var wire 1 9$ in [1] $end
$var wire 1 I% sram [0] $end
$var wire 1 J% sram [1] $end
$var wire 1 +( sram_inv [0] $end
$var wire 1 ,( sram_inv [1] $end
$var wire 1 o$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 W? mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 X? mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 Y? SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 Z? SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 [? SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 \? BUF_net_155 $end

$scope module mux_l1_in_0_ $end
$var wire 1 _# in [0] $end
$var wire 1 9$ in [1] $end
$var wire 1 I% mem [0] $end
$var wire 1 Y? mem_inv [0] $end
$var wire 1 W? out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 W? X $end
$var wire 1 9$ A0 $end
$var wire 1 _# A1 $end
$var wire 1 I% S $end
$var supply1 1 ]? VPWR $end
$var supply0 1 ^? VGND $end
$var supply1 1 _? VPB $end
$var supply0 1 `? VNB $end

$scope module base $end
$var wire 1 W? X $end
$var wire 1 9$ A0 $end
$var wire 1 _# A1 $end
$var wire 1 I% S $end
$var wire 1 a? mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 W? in [0] $end
$var wire 1 Z? in [1] $end
$var wire 1 J% mem [0] $end
$var wire 1 [? mem_inv [0] $end
$var wire 1 X? out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 X? X $end
$var wire 1 p' A0 $end
$var wire 1 W? A1 $end
$var wire 1 J% S $end
$var supply1 1 b? VPWR $end
$var supply0 1 c? VGND $end
$var supply1 1 d? VPB $end
$var supply0 1 e? VNB $end

$scope module base $end
$var wire 1 X? X $end
$var wire 1 p' A0 $end
$var wire 1 W? A1 $end
$var wire 1 J% S $end
$var wire 1 f? mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_154 $end
$var wire 1 o$ Y $end
$var wire 1 \? A $end
$var supply1 1 g? VPWR $end
$var supply0 1 h? VGND $end
$var supply1 1 i? VPB $end
$var supply0 1 j? VNB $end

$scope module base $end
$var wire 1 o$ Y $end
$var wire 1 \? A $end
$var wire 1 k? not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_155 $end
$var wire 1 \? Y $end
$var wire 1 X? A $end
$var supply1 1 l? VPWR $end
$var supply0 1 m? VGND $end
$var supply1 1 n? VPB $end
$var supply0 1 o? VNB $end

$scope module base $end
$var wire 1 \? Y $end
$var wire 1 X? A $end
$var wire 1 p? not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_43 $end
$var wire 1 `# in [0] $end
$var wire 1 :$ in [1] $end
$var wire 1 K% sram [0] $end
$var wire 1 L% sram [1] $end
$var wire 1 -( sram_inv [0] $end
$var wire 1 .( sram_inv [1] $end
$var wire 1 p$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 q? mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 r? mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 s? SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 t? SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 u? SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 v? BUF_net_157 $end

$scope module mux_l1_in_0_ $end
$var wire 1 `# in [0] $end
$var wire 1 :$ in [1] $end
$var wire 1 K% mem [0] $end
$var wire 1 s? mem_inv [0] $end
$var wire 1 q? out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 q? X $end
$var wire 1 :$ A0 $end
$var wire 1 `# A1 $end
$var wire 1 K% S $end
$var supply1 1 w? VPWR $end
$var supply0 1 x? VGND $end
$var supply1 1 y? VPB $end
$var supply0 1 z? VNB $end

$scope module base $end
$var wire 1 q? X $end
$var wire 1 :$ A0 $end
$var wire 1 `# A1 $end
$var wire 1 K% S $end
$var wire 1 {? mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 q? in [0] $end
$var wire 1 t? in [1] $end
$var wire 1 L% mem [0] $end
$var wire 1 u? mem_inv [0] $end
$var wire 1 r? out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 r? X $end
$var wire 1 p' A0 $end
$var wire 1 q? A1 $end
$var wire 1 L% S $end
$var supply1 1 |? VPWR $end
$var supply0 1 }? VGND $end
$var supply1 1 ~? VPB $end
$var supply0 1 !@ VNB $end

$scope module base $end
$var wire 1 r? X $end
$var wire 1 p' A0 $end
$var wire 1 q? A1 $end
$var wire 1 L% S $end
$var wire 1 "@ mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_156 $end
$var wire 1 p$ Y $end
$var wire 1 v? A $end
$var supply1 1 #@ VPWR $end
$var supply0 1 $@ VGND $end
$var supply1 1 %@ VPB $end
$var supply0 1 &@ VNB $end

$scope module base $end
$var wire 1 p$ Y $end
$var wire 1 v? A $end
$var wire 1 '@ not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_157 $end
$var wire 1 v? Y $end
$var wire 1 r? A $end
$var supply1 1 (@ VPWR $end
$var supply0 1 )@ VGND $end
$var supply1 1 *@ VPB $end
$var supply0 1 +@ VNB $end

$scope module base $end
$var wire 1 v? Y $end
$var wire 1 r? A $end
$var wire 1 ,@ not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_45 $end
$var wire 1 a# in [0] $end
$var wire 1 3$ in [1] $end
$var wire 1 O% sram [0] $end
$var wire 1 P% sram [1] $end
$var wire 1 /( sram_inv [0] $end
$var wire 1 0( sram_inv [1] $end
$var wire 1 q$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 -@ mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 .@ mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 /@ SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 0@ SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 1@ SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 2@ BUF_net_159 $end

$scope module mux_l1_in_0_ $end
$var wire 1 a# in [0] $end
$var wire 1 3$ in [1] $end
$var wire 1 O% mem [0] $end
$var wire 1 /@ mem_inv [0] $end
$var wire 1 -@ out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 -@ X $end
$var wire 1 3$ A0 $end
$var wire 1 a# A1 $end
$var wire 1 O% S $end
$var supply1 1 3@ VPWR $end
$var supply0 1 4@ VGND $end
$var supply1 1 5@ VPB $end
$var supply0 1 6@ VNB $end

$scope module base $end
$var wire 1 -@ X $end
$var wire 1 3$ A0 $end
$var wire 1 a# A1 $end
$var wire 1 O% S $end
$var wire 1 7@ mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 -@ in [0] $end
$var wire 1 0@ in [1] $end
$var wire 1 P% mem [0] $end
$var wire 1 1@ mem_inv [0] $end
$var wire 1 .@ out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 .@ X $end
$var wire 1 p' A0 $end
$var wire 1 -@ A1 $end
$var wire 1 P% S $end
$var supply1 1 8@ VPWR $end
$var supply0 1 9@ VGND $end
$var supply1 1 :@ VPB $end
$var supply0 1 ;@ VNB $end

$scope module base $end
$var wire 1 .@ X $end
$var wire 1 p' A0 $end
$var wire 1 -@ A1 $end
$var wire 1 P% S $end
$var wire 1 <@ mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_158 $end
$var wire 1 q$ Y $end
$var wire 1 2@ A $end
$var supply1 1 =@ VPWR $end
$var supply0 1 >@ VGND $end
$var supply1 1 ?@ VPB $end
$var supply0 1 @@ VNB $end

$scope module base $end
$var wire 1 q$ Y $end
$var wire 1 2@ A $end
$var wire 1 A@ not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_159 $end
$var wire 1 2@ Y $end
$var wire 1 .@ A $end
$var supply1 1 B@ VPWR $end
$var supply0 1 C@ VGND $end
$var supply1 1 D@ VPB $end
$var supply0 1 E@ VNB $end

$scope module base $end
$var wire 1 2@ Y $end
$var wire 1 .@ A $end
$var wire 1 F@ not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_47 $end
$var wire 1 b# in [0] $end
$var wire 1 4$ in [1] $end
$var wire 1 Q% sram [0] $end
$var wire 1 R% sram [1] $end
$var wire 1 1( sram_inv [0] $end
$var wire 1 2( sram_inv [1] $end
$var wire 1 r$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 G@ mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 H@ mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 I@ SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 J@ SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 K@ SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 L@ BUF_net_161 $end

$scope module mux_l1_in_0_ $end
$var wire 1 b# in [0] $end
$var wire 1 4$ in [1] $end
$var wire 1 Q% mem [0] $end
$var wire 1 I@ mem_inv [0] $end
$var wire 1 G@ out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 G@ X $end
$var wire 1 4$ A0 $end
$var wire 1 b# A1 $end
$var wire 1 Q% S $end
$var supply1 1 M@ VPWR $end
$var supply0 1 N@ VGND $end
$var supply1 1 O@ VPB $end
$var supply0 1 P@ VNB $end

$scope module base $end
$var wire 1 G@ X $end
$var wire 1 4$ A0 $end
$var wire 1 b# A1 $end
$var wire 1 Q% S $end
$var wire 1 Q@ mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 G@ in [0] $end
$var wire 1 J@ in [1] $end
$var wire 1 R% mem [0] $end
$var wire 1 K@ mem_inv [0] $end
$var wire 1 H@ out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 H@ X $end
$var wire 1 p' A0 $end
$var wire 1 G@ A1 $end
$var wire 1 R% S $end
$var supply1 1 R@ VPWR $end
$var supply0 1 S@ VGND $end
$var supply1 1 T@ VPB $end
$var supply0 1 U@ VNB $end

$scope module base $end
$var wire 1 H@ X $end
$var wire 1 p' A0 $end
$var wire 1 G@ A1 $end
$var wire 1 R% S $end
$var wire 1 V@ mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_160 $end
$var wire 1 r$ Y $end
$var wire 1 L@ A $end
$var supply1 1 W@ VPWR $end
$var supply0 1 X@ VGND $end
$var supply1 1 Y@ VPB $end
$var supply0 1 Z@ VNB $end

$scope module base $end
$var wire 1 r$ Y $end
$var wire 1 L@ A $end
$var wire 1 [@ not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_161 $end
$var wire 1 L@ Y $end
$var wire 1 H@ A $end
$var supply1 1 \@ VPWR $end
$var supply0 1 ]@ VGND $end
$var supply1 1 ^@ VPB $end
$var supply0 1 _@ VNB $end

$scope module base $end
$var wire 1 L@ Y $end
$var wire 1 H@ A $end
$var wire 1 `@ not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_49 $end
$var wire 1 c# in [0] $end
$var wire 1 5$ in [1] $end
$var wire 1 S% sram [0] $end
$var wire 1 T% sram [1] $end
$var wire 1 3( sram_inv [0] $end
$var wire 1 4( sram_inv [1] $end
$var wire 1 s$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 a@ mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 b@ mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 c@ SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 d@ SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 e@ SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 f@ BUF_net_163 $end

$scope module mux_l1_in_0_ $end
$var wire 1 c# in [0] $end
$var wire 1 5$ in [1] $end
$var wire 1 S% mem [0] $end
$var wire 1 c@ mem_inv [0] $end
$var wire 1 a@ out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 a@ X $end
$var wire 1 5$ A0 $end
$var wire 1 c# A1 $end
$var wire 1 S% S $end
$var supply1 1 g@ VPWR $end
$var supply0 1 h@ VGND $end
$var supply1 1 i@ VPB $end
$var supply0 1 j@ VNB $end

$scope module base $end
$var wire 1 a@ X $end
$var wire 1 5$ A0 $end
$var wire 1 c# A1 $end
$var wire 1 S% S $end
$var wire 1 k@ mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 a@ in [0] $end
$var wire 1 d@ in [1] $end
$var wire 1 T% mem [0] $end
$var wire 1 e@ mem_inv [0] $end
$var wire 1 b@ out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 b@ X $end
$var wire 1 p' A0 $end
$var wire 1 a@ A1 $end
$var wire 1 T% S $end
$var supply1 1 l@ VPWR $end
$var supply0 1 m@ VGND $end
$var supply1 1 n@ VPB $end
$var supply0 1 o@ VNB $end

$scope module base $end
$var wire 1 b@ X $end
$var wire 1 p' A0 $end
$var wire 1 a@ A1 $end
$var wire 1 T% S $end
$var wire 1 p@ mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_162 $end
$var wire 1 s$ Y $end
$var wire 1 f@ A $end
$var supply1 1 q@ VPWR $end
$var supply0 1 r@ VGND $end
$var supply1 1 s@ VPB $end
$var supply0 1 t@ VNB $end

$scope module base $end
$var wire 1 s$ Y $end
$var wire 1 f@ A $end
$var wire 1 u@ not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_163 $end
$var wire 1 f@ Y $end
$var wire 1 b@ A $end
$var supply1 1 v@ VPWR $end
$var supply0 1 w@ VGND $end
$var supply1 1 x@ VPB $end
$var supply0 1 y@ VNB $end

$scope module base $end
$var wire 1 f@ Y $end
$var wire 1 b@ A $end
$var wire 1 z@ not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_51 $end
$var wire 1 d# in [0] $end
$var wire 1 6$ in [1] $end
$var wire 1 U% sram [0] $end
$var wire 1 V% sram [1] $end
$var wire 1 5( sram_inv [0] $end
$var wire 1 6( sram_inv [1] $end
$var wire 1 t$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 {@ mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 |@ mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 }@ SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 ~@ SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 !A SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 "A BUF_net_165 $end

$scope module mux_l1_in_0_ $end
$var wire 1 d# in [0] $end
$var wire 1 6$ in [1] $end
$var wire 1 U% mem [0] $end
$var wire 1 }@ mem_inv [0] $end
$var wire 1 {@ out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 {@ X $end
$var wire 1 6$ A0 $end
$var wire 1 d# A1 $end
$var wire 1 U% S $end
$var supply1 1 #A VPWR $end
$var supply0 1 $A VGND $end
$var supply1 1 %A VPB $end
$var supply0 1 &A VNB $end

$scope module base $end
$var wire 1 {@ X $end
$var wire 1 6$ A0 $end
$var wire 1 d# A1 $end
$var wire 1 U% S $end
$var wire 1 'A mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 {@ in [0] $end
$var wire 1 ~@ in [1] $end
$var wire 1 V% mem [0] $end
$var wire 1 !A mem_inv [0] $end
$var wire 1 |@ out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 |@ X $end
$var wire 1 p' A0 $end
$var wire 1 {@ A1 $end
$var wire 1 V% S $end
$var supply1 1 (A VPWR $end
$var supply0 1 )A VGND $end
$var supply1 1 *A VPB $end
$var supply0 1 +A VNB $end

$scope module base $end
$var wire 1 |@ X $end
$var wire 1 p' A0 $end
$var wire 1 {@ A1 $end
$var wire 1 V% S $end
$var wire 1 ,A mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_164 $end
$var wire 1 t$ Y $end
$var wire 1 "A A $end
$var supply1 1 -A VPWR $end
$var supply0 1 .A VGND $end
$var supply1 1 /A VPB $end
$var supply0 1 0A VNB $end

$scope module base $end
$var wire 1 t$ Y $end
$var wire 1 "A A $end
$var wire 1 1A not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_165 $end
$var wire 1 "A Y $end
$var wire 1 |@ A $end
$var supply1 1 2A VPWR $end
$var supply0 1 3A VGND $end
$var supply1 1 4A VPB $end
$var supply0 1 5A VNB $end

$scope module base $end
$var wire 1 "A Y $end
$var wire 1 |@ A $end
$var wire 1 6A not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_55 $end
$var wire 1 f# in [0] $end
$var wire 1 8$ in [1] $end
$var wire 1 W% sram [0] $end
$var wire 1 X% sram [1] $end
$var wire 1 7( sram_inv [0] $end
$var wire 1 8( sram_inv [1] $end
$var wire 1 v$ out [0] $end
$var wire 1 R' p0 $end
$var wire 1 7A mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 8A mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 9A SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 :A SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 ;A SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 <A BUF_net_167 $end

$scope module mux_l1_in_0_ $end
$var wire 1 f# in [0] $end
$var wire 1 8$ in [1] $end
$var wire 1 W% mem [0] $end
$var wire 1 9A mem_inv [0] $end
$var wire 1 7A out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 7A X $end
$var wire 1 8$ A0 $end
$var wire 1 f# A1 $end
$var wire 1 W% S $end
$var supply1 1 =A VPWR $end
$var supply0 1 >A VGND $end
$var supply1 1 ?A VPB $end
$var supply0 1 @A VNB $end

$scope module base $end
$var wire 1 7A X $end
$var wire 1 8$ A0 $end
$var wire 1 f# A1 $end
$var wire 1 W% S $end
$var wire 1 AA mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 7A in [0] $end
$var wire 1 :A in [1] $end
$var wire 1 X% mem [0] $end
$var wire 1 ;A mem_inv [0] $end
$var wire 1 8A out [0] $end
$var wire 1 R' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 8A X $end
$var wire 1 R' A0 $end
$var wire 1 7A A1 $end
$var wire 1 X% S $end
$var supply1 1 BA VPWR $end
$var supply0 1 CA VGND $end
$var supply1 1 DA VPB $end
$var supply0 1 EA VNB $end

$scope module base $end
$var wire 1 8A X $end
$var wire 1 R' A0 $end
$var wire 1 7A A1 $end
$var wire 1 X% S $end
$var wire 1 FA mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_166 $end
$var wire 1 v$ Y $end
$var wire 1 <A A $end
$var supply1 1 GA VPWR $end
$var supply0 1 HA VGND $end
$var supply1 1 IA VPB $end
$var supply0 1 JA VNB $end

$scope module base $end
$var wire 1 v$ Y $end
$var wire 1 <A A $end
$var wire 1 KA not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_167 $end
$var wire 1 <A Y $end
$var wire 1 8A A $end
$var supply1 1 LA VPWR $end
$var supply0 1 MA VGND $end
$var supply1 1 NA VPB $end
$var supply0 1 OA VNB $end

$scope module base $end
$var wire 1 <A Y $end
$var wire 1 8A A $end
$var wire 1 PA not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_57 $end
$var wire 1 g# in [0] $end
$var wire 1 9$ in [1] $end
$var wire 1 Y% sram [0] $end
$var wire 1 Z% sram [1] $end
$var wire 1 9( sram_inv [0] $end
$var wire 1 :( sram_inv [1] $end
$var wire 1 w$ out [0] $end
$var wire 1 R' p0 $end
$var wire 1 QA mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 RA mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 SA SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 TA SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 UA SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 VA BUF_net_169 $end

$scope module mux_l1_in_0_ $end
$var wire 1 g# in [0] $end
$var wire 1 9$ in [1] $end
$var wire 1 Y% mem [0] $end
$var wire 1 SA mem_inv [0] $end
$var wire 1 QA out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 QA X $end
$var wire 1 9$ A0 $end
$var wire 1 g# A1 $end
$var wire 1 Y% S $end
$var supply1 1 WA VPWR $end
$var supply0 1 XA VGND $end
$var supply1 1 YA VPB $end
$var supply0 1 ZA VNB $end

$scope module base $end
$var wire 1 QA X $end
$var wire 1 9$ A0 $end
$var wire 1 g# A1 $end
$var wire 1 Y% S $end
$var wire 1 [A mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 QA in [0] $end
$var wire 1 TA in [1] $end
$var wire 1 Z% mem [0] $end
$var wire 1 UA mem_inv [0] $end
$var wire 1 RA out [0] $end
$var wire 1 R' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 RA X $end
$var wire 1 R' A0 $end
$var wire 1 QA A1 $end
$var wire 1 Z% S $end
$var supply1 1 \A VPWR $end
$var supply0 1 ]A VGND $end
$var supply1 1 ^A VPB $end
$var supply0 1 _A VNB $end

$scope module base $end
$var wire 1 RA X $end
$var wire 1 R' A0 $end
$var wire 1 QA A1 $end
$var wire 1 Z% S $end
$var wire 1 `A mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_168 $end
$var wire 1 w$ Y $end
$var wire 1 VA A $end
$var supply1 1 aA VPWR $end
$var supply0 1 bA VGND $end
$var supply1 1 cA VPB $end
$var supply0 1 dA VNB $end

$scope module base $end
$var wire 1 w$ Y $end
$var wire 1 VA A $end
$var wire 1 eA not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_169 $end
$var wire 1 VA Y $end
$var wire 1 RA A $end
$var supply1 1 fA VPWR $end
$var supply0 1 gA VGND $end
$var supply1 1 hA VPB $end
$var supply0 1 iA VNB $end

$scope module base $end
$var wire 1 VA Y $end
$var wire 1 RA A $end
$var wire 1 jA not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_59 $end
$var wire 1 h# in [0] $end
$var wire 1 :$ in [1] $end
$var wire 1 [% sram [0] $end
$var wire 1 \% sram [1] $end
$var wire 1 ;( sram_inv [0] $end
$var wire 1 <( sram_inv [1] $end
$var wire 1 x$ out [0] $end
$var wire 1 R' p0 $end
$var wire 1 kA mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 lA mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 mA SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 nA SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 oA SYNOPSYS_UNCONNECTED_3 $end

$scope module sky130_fd_sc_hd__buf_4_0_ $end
$var wire 1 x$ X $end
$var wire 1 lA A $end
$var supply1 1 pA VPWR $end
$var supply0 1 qA VGND $end
$var supply1 1 rA VPB $end
$var supply0 1 sA VNB $end

$scope module base $end
$var wire 1 x$ X $end
$var wire 1 lA A $end
$var wire 1 tA buf0_out_X $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 h# in [0] $end
$var wire 1 :$ in [1] $end
$var wire 1 [% mem [0] $end
$var wire 1 mA mem_inv [0] $end
$var wire 1 kA out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 kA X $end
$var wire 1 :$ A0 $end
$var wire 1 h# A1 $end
$var wire 1 [% S $end
$var supply1 1 uA VPWR $end
$var supply0 1 vA VGND $end
$var supply1 1 wA VPB $end
$var supply0 1 xA VNB $end

$scope module base $end
$var wire 1 kA X $end
$var wire 1 :$ A0 $end
$var wire 1 h# A1 $end
$var wire 1 [% S $end
$var wire 1 yA mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 kA in [0] $end
$var wire 1 nA in [1] $end
$var wire 1 \% mem [0] $end
$var wire 1 oA mem_inv [0] $end
$var wire 1 lA out [0] $end
$var wire 1 R' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 lA X $end
$var wire 1 R' A0 $end
$var wire 1 kA A1 $end
$var wire 1 \% S $end
$var supply1 1 zA VPWR $end
$var supply0 1 {A VGND $end
$var supply1 1 |A VPB $end
$var supply0 1 }A VNB $end

$scope module base $end
$var wire 1 lA X $end
$var wire 1 R' A0 $end
$var wire 1 kA A1 $end
$var wire 1 \% S $end
$var wire 1 ~A mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_13 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 t& ccff_head [0] $end
$var wire 1 k% ccff_tail [0] $end
$var wire 1 !% mem_out [0] $end
$var wire 1 "% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 !% Q $end
$var wire 1 }$ CLK $end
$var wire 1 t& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 !B VPWR $end
$var supply0 1 "B VGND $end
$var supply1 1 #B VPB $end
$var supply0 1 $B VNB $end

$scope module base $end
$var wire 1 !% Q $end
$var wire 1 }$ CLK $end
$var wire 1 t& D $end
$var wire 1 K# RESET_B $end
$var wire 1 %B buf_Q $end
$var wire 1 &B RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 "% Q $end
$var wire 1 }$ CLK $end
$var wire 1 !% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 'B VPWR $end
$var supply0 1 (B VGND $end
$var supply1 1 )B VPB $end
$var supply0 1 *B VNB $end

$scope module base $end
$var wire 1 "% Q $end
$var wire 1 }$ CLK $end
$var wire 1 !% D $end
$var wire 1 K# RESET_B $end
$var wire 1 +B buf_Q $end
$var wire 1 ,B RESET $end
$upscope $end
$upscope $end

$scope module FTB_37__36 $end
$var wire 1 k% X $end
$var wire 1 "% A $end
$var supply1 1 -B VPWR $end
$var supply0 1 .B VGND $end
$var supply1 1 /B VPB $end
$var supply0 1 0B VNB $end

$scope module base $end
$var wire 1 k% X $end
$var wire 1 "% A $end
$var wire 1 1B buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_15 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 k% ccff_head [0] $end
$var wire 1 v% ccff_tail [0] $end
$var wire 1 7% mem_out [0] $end
$var wire 1 8% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 7% Q $end
$var wire 1 }$ CLK $end
$var wire 1 k% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 2B VPWR $end
$var supply0 1 3B VGND $end
$var supply1 1 4B VPB $end
$var supply0 1 5B VNB $end

$scope module base $end
$var wire 1 7% Q $end
$var wire 1 }$ CLK $end
$var wire 1 k% D $end
$var wire 1 K# RESET_B $end
$var wire 1 6B buf_Q $end
$var wire 1 7B RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 8% Q $end
$var wire 1 }$ CLK $end
$var wire 1 7% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 8B VPWR $end
$var supply0 1 9B VGND $end
$var supply1 1 :B VPB $end
$var supply0 1 ;B VNB $end

$scope module base $end
$var wire 1 8% Q $end
$var wire 1 }$ CLK $end
$var wire 1 7% D $end
$var wire 1 K# RESET_B $end
$var wire 1 <B buf_Q $end
$var wire 1 =B RESET $end
$upscope $end
$upscope $end

$scope module FTB_38__37 $end
$var wire 1 v% X $end
$var wire 1 8% A $end
$var supply1 1 >B VPWR $end
$var supply0 1 ?B VGND $end
$var supply1 1 @B VPB $end
$var supply0 1 AB VNB $end

$scope module base $end
$var wire 1 v% X $end
$var wire 1 8% A $end
$var wire 1 BB buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_17 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 v% ccff_head [0] $end
$var wire 1 #& ccff_tail [0] $end
$var wire 1 M% mem_out [0] $end
$var wire 1 N% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 M% Q $end
$var wire 1 }$ CLK $end
$var wire 1 v% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 CB VPWR $end
$var supply0 1 DB VGND $end
$var supply1 1 EB VPB $end
$var supply0 1 FB VNB $end

$scope module base $end
$var wire 1 M% Q $end
$var wire 1 }$ CLK $end
$var wire 1 v% D $end
$var wire 1 K# RESET_B $end
$var wire 1 GB buf_Q $end
$var wire 1 HB RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 N% Q $end
$var wire 1 }$ CLK $end
$var wire 1 M% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 IB VPWR $end
$var supply0 1 JB VGND $end
$var supply1 1 KB VPB $end
$var supply0 1 LB VNB $end

$scope module base $end
$var wire 1 N% Q $end
$var wire 1 }$ CLK $end
$var wire 1 M% D $end
$var wire 1 K# RESET_B $end
$var wire 1 MB buf_Q $end
$var wire 1 NB RESET $end
$upscope $end
$upscope $end

$scope module FTB_39__38 $end
$var wire 1 #& X $end
$var wire 1 N% A $end
$var supply1 1 OB VPWR $end
$var supply0 1 PB VGND $end
$var supply1 1 QB VPB $end
$var supply0 1 RB VNB $end

$scope module base $end
$var wire 1 #& X $end
$var wire 1 N% A $end
$var wire 1 SB buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_19 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 #& ccff_head [0] $end
$var wire 1 *& ccff_tail [0] $end
$var wire 1 ]% mem_out [0] $end
$var wire 1 ^% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 ]% Q $end
$var wire 1 }$ CLK $end
$var wire 1 #& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 TB VPWR $end
$var supply0 1 UB VGND $end
$var supply1 1 VB VPB $end
$var supply0 1 WB VNB $end

$scope module base $end
$var wire 1 ]% Q $end
$var wire 1 }$ CLK $end
$var wire 1 #& D $end
$var wire 1 K# RESET_B $end
$var wire 1 XB buf_Q $end
$var wire 1 YB RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 ^% Q $end
$var wire 1 }$ CLK $end
$var wire 1 ]% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 ZB VPWR $end
$var supply0 1 [B VGND $end
$var supply1 1 \B VPB $end
$var supply0 1 ]B VNB $end

$scope module base $end
$var wire 1 ^% Q $end
$var wire 1 }$ CLK $end
$var wire 1 ]% D $end
$var wire 1 K# RESET_B $end
$var wire 1 ^B buf_Q $end
$var wire 1 _B RESET $end
$upscope $end
$upscope $end

$scope module FTB_40__39 $end
$var wire 1 *& X $end
$var wire 1 ^% A $end
$var supply1 1 `B VPWR $end
$var supply0 1 aB VGND $end
$var supply1 1 bB VPB $end
$var supply0 1 cB VNB $end

$scope module base $end
$var wire 1 *& X $end
$var wire 1 ^% A $end
$var wire 1 dB buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_21 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 *& ccff_head [0] $end
$var wire 1 +& ccff_tail [0] $end
$var wire 1 _% mem_out [0] $end
$var wire 1 `% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 _% Q $end
$var wire 1 }$ CLK $end
$var wire 1 *& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 eB VPWR $end
$var supply0 1 fB VGND $end
$var supply1 1 gB VPB $end
$var supply0 1 hB VNB $end

$scope module base $end
$var wire 1 _% Q $end
$var wire 1 }$ CLK $end
$var wire 1 *& D $end
$var wire 1 K# RESET_B $end
$var wire 1 iB buf_Q $end
$var wire 1 jB RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 `% Q $end
$var wire 1 }$ CLK $end
$var wire 1 _% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 kB VPWR $end
$var supply0 1 lB VGND $end
$var supply1 1 mB VPB $end
$var supply0 1 nB VNB $end

$scope module base $end
$var wire 1 `% Q $end
$var wire 1 }$ CLK $end
$var wire 1 _% D $end
$var wire 1 K# RESET_B $end
$var wire 1 oB buf_Q $end
$var wire 1 pB RESET $end
$upscope $end
$upscope $end

$scope module FTB_41__40 $end
$var wire 1 +& X $end
$var wire 1 `% A $end
$var supply1 1 qB VPWR $end
$var supply0 1 rB VGND $end
$var supply1 1 sB VPB $end
$var supply0 1 tB VNB $end

$scope module base $end
$var wire 1 +& X $end
$var wire 1 `% A $end
$var wire 1 uB buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_23 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 +& ccff_head [0] $end
$var wire 1 ,& ccff_tail [0] $end
$var wire 1 a% mem_out [0] $end
$var wire 1 b% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 a% Q $end
$var wire 1 }$ CLK $end
$var wire 1 +& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 vB VPWR $end
$var supply0 1 wB VGND $end
$var supply1 1 xB VPB $end
$var supply0 1 yB VNB $end

$scope module base $end
$var wire 1 a% Q $end
$var wire 1 }$ CLK $end
$var wire 1 +& D $end
$var wire 1 K# RESET_B $end
$var wire 1 zB buf_Q $end
$var wire 1 {B RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 b% Q $end
$var wire 1 }$ CLK $end
$var wire 1 a% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 |B VPWR $end
$var supply0 1 }B VGND $end
$var supply1 1 ~B VPB $end
$var supply0 1 !C VNB $end

$scope module base $end
$var wire 1 b% Q $end
$var wire 1 }$ CLK $end
$var wire 1 a% D $end
$var wire 1 K# RESET_B $end
$var wire 1 "C buf_Q $end
$var wire 1 #C RESET $end
$upscope $end
$upscope $end

$scope module FTB_42__41 $end
$var wire 1 ,& X $end
$var wire 1 b% A $end
$var supply1 1 $C VPWR $end
$var supply0 1 %C VGND $end
$var supply1 1 &C VPB $end
$var supply0 1 'C VNB $end

$scope module base $end
$var wire 1 ,& X $end
$var wire 1 b% A $end
$var wire 1 (C buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_25 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 ,& ccff_head [0] $end
$var wire 1 -& ccff_tail [0] $end
$var wire 1 c% mem_out [0] $end
$var wire 1 d% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 c% Q $end
$var wire 1 }$ CLK $end
$var wire 1 ,& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 )C VPWR $end
$var supply0 1 *C VGND $end
$var supply1 1 +C VPB $end
$var supply0 1 ,C VNB $end

$scope module base $end
$var wire 1 c% Q $end
$var wire 1 }$ CLK $end
$var wire 1 ,& D $end
$var wire 1 K# RESET_B $end
$var wire 1 -C buf_Q $end
$var wire 1 .C RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 d% Q $end
$var wire 1 }$ CLK $end
$var wire 1 c% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 /C VPWR $end
$var supply0 1 0C VGND $end
$var supply1 1 1C VPB $end
$var supply0 1 2C VNB $end

$scope module base $end
$var wire 1 d% Q $end
$var wire 1 }$ CLK $end
$var wire 1 c% D $end
$var wire 1 K# RESET_B $end
$var wire 1 3C buf_Q $end
$var wire 1 4C RESET $end
$upscope $end
$upscope $end

$scope module FTB_43__42 $end
$var wire 1 -& X $end
$var wire 1 d% A $end
$var supply1 1 5C VPWR $end
$var supply0 1 6C VGND $end
$var supply1 1 7C VPB $end
$var supply0 1 8C VNB $end

$scope module base $end
$var wire 1 -& X $end
$var wire 1 d% A $end
$var wire 1 9C buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_27 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 -& ccff_head [0] $end
$var wire 1 .& ccff_tail [0] $end
$var wire 1 e% mem_out [0] $end
$var wire 1 f% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 e% Q $end
$var wire 1 }$ CLK $end
$var wire 1 -& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 :C VPWR $end
$var supply0 1 ;C VGND $end
$var supply1 1 <C VPB $end
$var supply0 1 =C VNB $end

$scope module base $end
$var wire 1 e% Q $end
$var wire 1 }$ CLK $end
$var wire 1 -& D $end
$var wire 1 K# RESET_B $end
$var wire 1 >C buf_Q $end
$var wire 1 ?C RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 f% Q $end
$var wire 1 }$ CLK $end
$var wire 1 e% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 @C VPWR $end
$var supply0 1 AC VGND $end
$var supply1 1 BC VPB $end
$var supply0 1 CC VNB $end

$scope module base $end
$var wire 1 f% Q $end
$var wire 1 }$ CLK $end
$var wire 1 e% D $end
$var wire 1 K# RESET_B $end
$var wire 1 DC buf_Q $end
$var wire 1 EC RESET $end
$upscope $end
$upscope $end

$scope module FTB_44__43 $end
$var wire 1 .& X $end
$var wire 1 f% A $end
$var supply1 1 FC VPWR $end
$var supply0 1 GC VGND $end
$var supply1 1 HC VPB $end
$var supply0 1 IC VNB $end

$scope module base $end
$var wire 1 .& X $end
$var wire 1 f% A $end
$var wire 1 JC buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_39 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 9& ccff_head [0] $end
$var wire 1 /& ccff_tail [0] $end
$var wire 1 g% mem_out [0] $end
$var wire 1 h% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 g% Q $end
$var wire 1 }$ CLK $end
$var wire 1 9& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 KC VPWR $end
$var supply0 1 LC VGND $end
$var supply1 1 MC VPB $end
$var supply0 1 NC VNB $end

$scope module base $end
$var wire 1 g% Q $end
$var wire 1 }$ CLK $end
$var wire 1 9& D $end
$var wire 1 K# RESET_B $end
$var wire 1 OC buf_Q $end
$var wire 1 PC RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 h% Q $end
$var wire 1 }$ CLK $end
$var wire 1 g% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 QC VPWR $end
$var supply0 1 RC VGND $end
$var supply1 1 SC VPB $end
$var supply0 1 TC VNB $end

$scope module base $end
$var wire 1 h% Q $end
$var wire 1 }$ CLK $end
$var wire 1 g% D $end
$var wire 1 K# RESET_B $end
$var wire 1 UC buf_Q $end
$var wire 1 VC RESET $end
$upscope $end
$upscope $end

$scope module FTB_45__44 $end
$var wire 1 /& X $end
$var wire 1 h% A $end
$var supply1 1 WC VPWR $end
$var supply0 1 XC VGND $end
$var supply1 1 YC VPB $end
$var supply0 1 ZC VNB $end

$scope module base $end
$var wire 1 /& X $end
$var wire 1 h% A $end
$var wire 1 [C buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_41 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 /& ccff_head [0] $end
$var wire 1 0& ccff_tail [0] $end
$var wire 1 i% mem_out [0] $end
$var wire 1 j% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 i% Q $end
$var wire 1 }$ CLK $end
$var wire 1 /& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 \C VPWR $end
$var supply0 1 ]C VGND $end
$var supply1 1 ^C VPB $end
$var supply0 1 _C VNB $end

$scope module base $end
$var wire 1 i% Q $end
$var wire 1 }$ CLK $end
$var wire 1 /& D $end
$var wire 1 K# RESET_B $end
$var wire 1 `C buf_Q $end
$var wire 1 aC RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 j% Q $end
$var wire 1 }$ CLK $end
$var wire 1 i% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 bC VPWR $end
$var supply0 1 cC VGND $end
$var supply1 1 dC VPB $end
$var supply0 1 eC VNB $end

$scope module base $end
$var wire 1 j% Q $end
$var wire 1 }$ CLK $end
$var wire 1 i% D $end
$var wire 1 K# RESET_B $end
$var wire 1 fC buf_Q $end
$var wire 1 gC RESET $end
$upscope $end
$upscope $end

$scope module FTB_46__45 $end
$var wire 1 0& X $end
$var wire 1 j% A $end
$var supply1 1 hC VPWR $end
$var supply0 1 iC VGND $end
$var supply1 1 jC VPB $end
$var supply0 1 kC VNB $end

$scope module base $end
$var wire 1 0& X $end
$var wire 1 j% A $end
$var wire 1 lC buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_43 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 0& ccff_head [0] $end
$var wire 1 l% ccff_tail [0] $end
$var wire 1 #% mem_out [0] $end
$var wire 1 $% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 #% Q $end
$var wire 1 }$ CLK $end
$var wire 1 0& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 mC VPWR $end
$var supply0 1 nC VGND $end
$var supply1 1 oC VPB $end
$var supply0 1 pC VNB $end

$scope module base $end
$var wire 1 #% Q $end
$var wire 1 }$ CLK $end
$var wire 1 0& D $end
$var wire 1 K# RESET_B $end
$var wire 1 qC buf_Q $end
$var wire 1 rC RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 $% Q $end
$var wire 1 }$ CLK $end
$var wire 1 #% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 sC VPWR $end
$var supply0 1 tC VGND $end
$var supply1 1 uC VPB $end
$var supply0 1 vC VNB $end

$scope module base $end
$var wire 1 $% Q $end
$var wire 1 }$ CLK $end
$var wire 1 #% D $end
$var wire 1 K# RESET_B $end
$var wire 1 wC buf_Q $end
$var wire 1 xC RESET $end
$upscope $end
$upscope $end

$scope module FTB_47__46 $end
$var wire 1 l% X $end
$var wire 1 $% A $end
$var supply1 1 yC VPWR $end
$var supply0 1 zC VGND $end
$var supply1 1 {C VPB $end
$var supply0 1 |C VNB $end

$scope module base $end
$var wire 1 l% X $end
$var wire 1 $% A $end
$var wire 1 }C buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_47 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 :& ccff_head [0] $end
$var wire 1 m% ccff_tail [0] $end
$var wire 1 %% mem_out [0] $end
$var wire 1 &% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 %% Q $end
$var wire 1 }$ CLK $end
$var wire 1 :& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 ~C VPWR $end
$var supply0 1 !D VGND $end
$var supply1 1 "D VPB $end
$var supply0 1 #D VNB $end

$scope module base $end
$var wire 1 %% Q $end
$var wire 1 }$ CLK $end
$var wire 1 :& D $end
$var wire 1 K# RESET_B $end
$var wire 1 $D buf_Q $end
$var wire 1 %D RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 &% Q $end
$var wire 1 }$ CLK $end
$var wire 1 %% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 &D VPWR $end
$var supply0 1 'D VGND $end
$var supply1 1 (D VPB $end
$var supply0 1 )D VNB $end

$scope module base $end
$var wire 1 &% Q $end
$var wire 1 }$ CLK $end
$var wire 1 %% D $end
$var wire 1 K# RESET_B $end
$var wire 1 *D buf_Q $end
$var wire 1 +D RESET $end
$upscope $end
$upscope $end

$scope module FTB_48__47 $end
$var wire 1 m% X $end
$var wire 1 &% A $end
$var supply1 1 ,D VPWR $end
$var supply0 1 -D VGND $end
$var supply1 1 .D VPB $end
$var supply0 1 /D VNB $end

$scope module base $end
$var wire 1 m% X $end
$var wire 1 &% A $end
$var wire 1 0D buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_49 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 m% ccff_head [0] $end
$var wire 1 n% ccff_tail [0] $end
$var wire 1 '% mem_out [0] $end
$var wire 1 (% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 '% Q $end
$var wire 1 }$ CLK $end
$var wire 1 m% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 1D VPWR $end
$var supply0 1 2D VGND $end
$var supply1 1 3D VPB $end
$var supply0 1 4D VNB $end

$scope module base $end
$var wire 1 '% Q $end
$var wire 1 }$ CLK $end
$var wire 1 m% D $end
$var wire 1 K# RESET_B $end
$var wire 1 5D buf_Q $end
$var wire 1 6D RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 (% Q $end
$var wire 1 }$ CLK $end
$var wire 1 '% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 7D VPWR $end
$var supply0 1 8D VGND $end
$var supply1 1 9D VPB $end
$var supply0 1 :D VNB $end

$scope module base $end
$var wire 1 (% Q $end
$var wire 1 }$ CLK $end
$var wire 1 '% D $end
$var wire 1 K# RESET_B $end
$var wire 1 ;D buf_Q $end
$var wire 1 <D RESET $end
$upscope $end
$upscope $end

$scope module FTB_49__48 $end
$var wire 1 n% X $end
$var wire 1 (% A $end
$var supply1 1 =D VPWR $end
$var supply0 1 >D VGND $end
$var supply1 1 ?D VPB $end
$var supply0 1 @D VNB $end

$scope module base $end
$var wire 1 n% X $end
$var wire 1 (% A $end
$var wire 1 AD buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_51 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 n% ccff_head [0] $end
$var wire 1 o% ccff_tail [0] $end
$var wire 1 )% mem_out [0] $end
$var wire 1 *% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 )% Q $end
$var wire 1 }$ CLK $end
$var wire 1 n% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 BD VPWR $end
$var supply0 1 CD VGND $end
$var supply1 1 DD VPB $end
$var supply0 1 ED VNB $end

$scope module base $end
$var wire 1 )% Q $end
$var wire 1 }$ CLK $end
$var wire 1 n% D $end
$var wire 1 K# RESET_B $end
$var wire 1 FD buf_Q $end
$var wire 1 GD RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 *% Q $end
$var wire 1 }$ CLK $end
$var wire 1 )% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 HD VPWR $end
$var supply0 1 ID VGND $end
$var supply1 1 JD VPB $end
$var supply0 1 KD VNB $end

$scope module base $end
$var wire 1 *% Q $end
$var wire 1 }$ CLK $end
$var wire 1 )% D $end
$var wire 1 K# RESET_B $end
$var wire 1 LD buf_Q $end
$var wire 1 MD RESET $end
$upscope $end
$upscope $end

$scope module FTB_50__49 $end
$var wire 1 o% X $end
$var wire 1 *% A $end
$var supply1 1 ND VPWR $end
$var supply0 1 OD VGND $end
$var supply1 1 PD VPB $end
$var supply0 1 QD VNB $end

$scope module base $end
$var wire 1 o% X $end
$var wire 1 *% A $end
$var wire 1 RD buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_53 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 o% ccff_head [0] $end
$var wire 1 p% ccff_tail [0] $end
$var wire 1 +% mem_out [0] $end
$var wire 1 ,% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 +% Q $end
$var wire 1 }$ CLK $end
$var wire 1 o% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 SD VPWR $end
$var supply0 1 TD VGND $end
$var supply1 1 UD VPB $end
$var supply0 1 VD VNB $end

$scope module base $end
$var wire 1 +% Q $end
$var wire 1 }$ CLK $end
$var wire 1 o% D $end
$var wire 1 K# RESET_B $end
$var wire 1 WD buf_Q $end
$var wire 1 XD RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 ,% Q $end
$var wire 1 }$ CLK $end
$var wire 1 +% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 YD VPWR $end
$var supply0 1 ZD VGND $end
$var supply1 1 [D VPB $end
$var supply0 1 \D VNB $end

$scope module base $end
$var wire 1 ,% Q $end
$var wire 1 }$ CLK $end
$var wire 1 +% D $end
$var wire 1 K# RESET_B $end
$var wire 1 ]D buf_Q $end
$var wire 1 ^D RESET $end
$upscope $end
$upscope $end

$scope module FTB_51__50 $end
$var wire 1 p% X $end
$var wire 1 ,% A $end
$var supply1 1 _D VPWR $end
$var supply0 1 `D VGND $end
$var supply1 1 aD VPB $end
$var supply0 1 bD VNB $end

$scope module base $end
$var wire 1 p% X $end
$var wire 1 ,% A $end
$var wire 1 cD buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_13 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 o& ccff_head [0] $end
$var wire 1 q% ccff_tail [0] $end
$var wire 1 -% mem_out [0] $end
$var wire 1 .% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 -% Q $end
$var wire 1 }$ CLK $end
$var wire 1 o& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 dD VPWR $end
$var supply0 1 eD VGND $end
$var supply1 1 fD VPB $end
$var supply0 1 gD VNB $end

$scope module base $end
$var wire 1 -% Q $end
$var wire 1 }$ CLK $end
$var wire 1 o& D $end
$var wire 1 K# RESET_B $end
$var wire 1 hD buf_Q $end
$var wire 1 iD RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 .% Q $end
$var wire 1 }$ CLK $end
$var wire 1 -% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 jD VPWR $end
$var supply0 1 kD VGND $end
$var supply1 1 lD VPB $end
$var supply0 1 mD VNB $end

$scope module base $end
$var wire 1 .% Q $end
$var wire 1 }$ CLK $end
$var wire 1 -% D $end
$var wire 1 K# RESET_B $end
$var wire 1 nD buf_Q $end
$var wire 1 oD RESET $end
$upscope $end
$upscope $end

$scope module FTB_52__51 $end
$var wire 1 q% X $end
$var wire 1 .% A $end
$var supply1 1 pD VPWR $end
$var supply0 1 qD VGND $end
$var supply1 1 rD VPB $end
$var supply0 1 sD VNB $end

$scope module base $end
$var wire 1 q% X $end
$var wire 1 .% A $end
$var wire 1 tD buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_15 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 q% ccff_head [0] $end
$var wire 1 r% ccff_tail [0] $end
$var wire 1 /% mem_out [0] $end
$var wire 1 0% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 /% Q $end
$var wire 1 }$ CLK $end
$var wire 1 q% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 uD VPWR $end
$var supply0 1 vD VGND $end
$var supply1 1 wD VPB $end
$var supply0 1 xD VNB $end

$scope module base $end
$var wire 1 /% Q $end
$var wire 1 }$ CLK $end
$var wire 1 q% D $end
$var wire 1 K# RESET_B $end
$var wire 1 yD buf_Q $end
$var wire 1 zD RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 0% Q $end
$var wire 1 }$ CLK $end
$var wire 1 /% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 {D VPWR $end
$var supply0 1 |D VGND $end
$var supply1 1 }D VPB $end
$var supply0 1 ~D VNB $end

$scope module base $end
$var wire 1 0% Q $end
$var wire 1 }$ CLK $end
$var wire 1 /% D $end
$var wire 1 K# RESET_B $end
$var wire 1 !E buf_Q $end
$var wire 1 "E RESET $end
$upscope $end
$upscope $end

$scope module FTB_53__52 $end
$var wire 1 r% X $end
$var wire 1 0% A $end
$var supply1 1 #E VPWR $end
$var supply0 1 $E VGND $end
$var supply1 1 %E VPB $end
$var supply0 1 &E VNB $end

$scope module base $end
$var wire 1 r% X $end
$var wire 1 0% A $end
$var wire 1 'E buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_17 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 r% ccff_head [0] $end
$var wire 1 s% ccff_tail [0] $end
$var wire 1 1% mem_out [0] $end
$var wire 1 2% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 1% Q $end
$var wire 1 }$ CLK $end
$var wire 1 r% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 (E VPWR $end
$var supply0 1 )E VGND $end
$var supply1 1 *E VPB $end
$var supply0 1 +E VNB $end

$scope module base $end
$var wire 1 1% Q $end
$var wire 1 }$ CLK $end
$var wire 1 r% D $end
$var wire 1 K# RESET_B $end
$var wire 1 ,E buf_Q $end
$var wire 1 -E RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 2% Q $end
$var wire 1 }$ CLK $end
$var wire 1 1% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 .E VPWR $end
$var supply0 1 /E VGND $end
$var supply1 1 0E VPB $end
$var supply0 1 1E VNB $end

$scope module base $end
$var wire 1 2% Q $end
$var wire 1 }$ CLK $end
$var wire 1 1% D $end
$var wire 1 K# RESET_B $end
$var wire 1 2E buf_Q $end
$var wire 1 3E RESET $end
$upscope $end
$upscope $end

$scope module FTB_54__53 $end
$var wire 1 s% X $end
$var wire 1 2% A $end
$var supply1 1 4E VPWR $end
$var supply0 1 5E VGND $end
$var supply1 1 6E VPB $end
$var supply0 1 7E VNB $end

$scope module base $end
$var wire 1 s% X $end
$var wire 1 2% A $end
$var wire 1 8E buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_19 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 s% ccff_head [0] $end
$var wire 1 t% ccff_tail [0] $end
$var wire 1 3% mem_out [0] $end
$var wire 1 4% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 3% Q $end
$var wire 1 }$ CLK $end
$var wire 1 s% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 9E VPWR $end
$var supply0 1 :E VGND $end
$var supply1 1 ;E VPB $end
$var supply0 1 <E VNB $end

$scope module base $end
$var wire 1 3% Q $end
$var wire 1 }$ CLK $end
$var wire 1 s% D $end
$var wire 1 K# RESET_B $end
$var wire 1 =E buf_Q $end
$var wire 1 >E RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 4% Q $end
$var wire 1 }$ CLK $end
$var wire 1 3% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 ?E VPWR $end
$var supply0 1 @E VGND $end
$var supply1 1 AE VPB $end
$var supply0 1 BE VNB $end

$scope module base $end
$var wire 1 4% Q $end
$var wire 1 }$ CLK $end
$var wire 1 3% D $end
$var wire 1 K# RESET_B $end
$var wire 1 CE buf_Q $end
$var wire 1 DE RESET $end
$upscope $end
$upscope $end

$scope module FTB_55__54 $end
$var wire 1 t% X $end
$var wire 1 4% A $end
$var supply1 1 EE VPWR $end
$var supply0 1 FE VGND $end
$var supply1 1 GE VPB $end
$var supply0 1 HE VNB $end

$scope module base $end
$var wire 1 t% X $end
$var wire 1 4% A $end
$var wire 1 IE buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_21 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 t% ccff_head [0] $end
$var wire 1 u% ccff_tail [0] $end
$var wire 1 5% mem_out [0] $end
$var wire 1 6% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 5% Q $end
$var wire 1 }$ CLK $end
$var wire 1 t% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 JE VPWR $end
$var supply0 1 KE VGND $end
$var supply1 1 LE VPB $end
$var supply0 1 ME VNB $end

$scope module base $end
$var wire 1 5% Q $end
$var wire 1 }$ CLK $end
$var wire 1 t% D $end
$var wire 1 K# RESET_B $end
$var wire 1 NE buf_Q $end
$var wire 1 OE RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 6% Q $end
$var wire 1 }$ CLK $end
$var wire 1 5% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 PE VPWR $end
$var supply0 1 QE VGND $end
$var supply1 1 RE VPB $end
$var supply0 1 SE VNB $end

$scope module base $end
$var wire 1 6% Q $end
$var wire 1 }$ CLK $end
$var wire 1 5% D $end
$var wire 1 K# RESET_B $end
$var wire 1 TE buf_Q $end
$var wire 1 UE RESET $end
$upscope $end
$upscope $end

$scope module FTB_56__55 $end
$var wire 1 u% X $end
$var wire 1 6% A $end
$var supply1 1 VE VPWR $end
$var supply0 1 WE VGND $end
$var supply1 1 XE VPB $end
$var supply0 1 YE VNB $end

$scope module base $end
$var wire 1 u% X $end
$var wire 1 6% A $end
$var wire 1 ZE buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_23 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 u% ccff_head [0] $end
$var wire 1 w% ccff_tail [0] $end
$var wire 1 9% mem_out [0] $end
$var wire 1 :% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 9% Q $end
$var wire 1 }$ CLK $end
$var wire 1 u% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 [E VPWR $end
$var supply0 1 \E VGND $end
$var supply1 1 ]E VPB $end
$var supply0 1 ^E VNB $end

$scope module base $end
$var wire 1 9% Q $end
$var wire 1 }$ CLK $end
$var wire 1 u% D $end
$var wire 1 K# RESET_B $end
$var wire 1 _E buf_Q $end
$var wire 1 `E RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 :% Q $end
$var wire 1 }$ CLK $end
$var wire 1 9% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 aE VPWR $end
$var supply0 1 bE VGND $end
$var supply1 1 cE VPB $end
$var supply0 1 dE VNB $end

$scope module base $end
$var wire 1 :% Q $end
$var wire 1 }$ CLK $end
$var wire 1 9% D $end
$var wire 1 K# RESET_B $end
$var wire 1 eE buf_Q $end
$var wire 1 fE RESET $end
$upscope $end
$upscope $end

$scope module FTB_57__56 $end
$var wire 1 w% X $end
$var wire 1 :% A $end
$var supply1 1 gE VPWR $end
$var supply0 1 hE VGND $end
$var supply1 1 iE VPB $end
$var supply0 1 jE VNB $end

$scope module base $end
$var wire 1 w% X $end
$var wire 1 :% A $end
$var wire 1 kE buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_25 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 w% ccff_head [0] $end
$var wire 1 x% ccff_tail [0] $end
$var wire 1 ;% mem_out [0] $end
$var wire 1 <% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 ;% Q $end
$var wire 1 }$ CLK $end
$var wire 1 w% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 lE VPWR $end
$var supply0 1 mE VGND $end
$var supply1 1 nE VPB $end
$var supply0 1 oE VNB $end

$scope module base $end
$var wire 1 ;% Q $end
$var wire 1 }$ CLK $end
$var wire 1 w% D $end
$var wire 1 K# RESET_B $end
$var wire 1 pE buf_Q $end
$var wire 1 qE RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 <% Q $end
$var wire 1 }$ CLK $end
$var wire 1 ;% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 rE VPWR $end
$var supply0 1 sE VGND $end
$var supply1 1 tE VPB $end
$var supply0 1 uE VNB $end

$scope module base $end
$var wire 1 <% Q $end
$var wire 1 }$ CLK $end
$var wire 1 ;% D $end
$var wire 1 K# RESET_B $end
$var wire 1 vE buf_Q $end
$var wire 1 wE RESET $end
$upscope $end
$upscope $end

$scope module FTB_58__57 $end
$var wire 1 x% X $end
$var wire 1 <% A $end
$var supply1 1 xE VPWR $end
$var supply0 1 yE VGND $end
$var supply1 1 zE VPB $end
$var supply0 1 {E VNB $end

$scope module base $end
$var wire 1 x% X $end
$var wire 1 <% A $end
$var wire 1 |E buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_27 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 x% ccff_head [0] $end
$var wire 1 y% ccff_tail [0] $end
$var wire 1 =% mem_out [0] $end
$var wire 1 >% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 =% Q $end
$var wire 1 }$ CLK $end
$var wire 1 x% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 }E VPWR $end
$var supply0 1 ~E VGND $end
$var supply1 1 !F VPB $end
$var supply0 1 "F VNB $end

$scope module base $end
$var wire 1 =% Q $end
$var wire 1 }$ CLK $end
$var wire 1 x% D $end
$var wire 1 K# RESET_B $end
$var wire 1 #F buf_Q $end
$var wire 1 $F RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 >% Q $end
$var wire 1 }$ CLK $end
$var wire 1 =% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 %F VPWR $end
$var supply0 1 &F VGND $end
$var supply1 1 'F VPB $end
$var supply0 1 (F VNB $end

$scope module base $end
$var wire 1 >% Q $end
$var wire 1 }$ CLK $end
$var wire 1 =% D $end
$var wire 1 K# RESET_B $end
$var wire 1 )F buf_Q $end
$var wire 1 *F RESET $end
$upscope $end
$upscope $end

$scope module FTB_59__58 $end
$var wire 1 y% X $end
$var wire 1 >% A $end
$var supply1 1 +F VPWR $end
$var supply0 1 ,F VGND $end
$var supply1 1 -F VPB $end
$var supply0 1 .F VNB $end

$scope module base $end
$var wire 1 y% X $end
$var wire 1 >% A $end
$var wire 1 /F buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_31 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 ;& ccff_head [0] $end
$var wire 1 z% ccff_tail [0] $end
$var wire 1 ?% mem_out [0] $end
$var wire 1 @% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 ?% Q $end
$var wire 1 }$ CLK $end
$var wire 1 ;& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 0F VPWR $end
$var supply0 1 1F VGND $end
$var supply1 1 2F VPB $end
$var supply0 1 3F VNB $end

$scope module base $end
$var wire 1 ?% Q $end
$var wire 1 }$ CLK $end
$var wire 1 ;& D $end
$var wire 1 K# RESET_B $end
$var wire 1 4F buf_Q $end
$var wire 1 5F RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 @% Q $end
$var wire 1 }$ CLK $end
$var wire 1 ?% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 6F VPWR $end
$var supply0 1 7F VGND $end
$var supply1 1 8F VPB $end
$var supply0 1 9F VNB $end

$scope module base $end
$var wire 1 @% Q $end
$var wire 1 }$ CLK $end
$var wire 1 ?% D $end
$var wire 1 K# RESET_B $end
$var wire 1 :F buf_Q $end
$var wire 1 ;F RESET $end
$upscope $end
$upscope $end

$scope module FTB_60__59 $end
$var wire 1 z% X $end
$var wire 1 @% A $end
$var supply1 1 <F VPWR $end
$var supply0 1 =F VGND $end
$var supply1 1 >F VPB $end
$var supply0 1 ?F VNB $end

$scope module base $end
$var wire 1 z% X $end
$var wire 1 @% A $end
$var wire 1 @F buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_33 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 z% ccff_head [0] $end
$var wire 1 {% ccff_tail [0] $end
$var wire 1 A% mem_out [0] $end
$var wire 1 B% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 A% Q $end
$var wire 1 }$ CLK $end
$var wire 1 z% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 AF VPWR $end
$var supply0 1 BF VGND $end
$var supply1 1 CF VPB $end
$var supply0 1 DF VNB $end

$scope module base $end
$var wire 1 A% Q $end
$var wire 1 }$ CLK $end
$var wire 1 z% D $end
$var wire 1 K# RESET_B $end
$var wire 1 EF buf_Q $end
$var wire 1 FF RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 B% Q $end
$var wire 1 }$ CLK $end
$var wire 1 A% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 GF VPWR $end
$var supply0 1 HF VGND $end
$var supply1 1 IF VPB $end
$var supply0 1 JF VNB $end

$scope module base $end
$var wire 1 B% Q $end
$var wire 1 }$ CLK $end
$var wire 1 A% D $end
$var wire 1 K# RESET_B $end
$var wire 1 KF buf_Q $end
$var wire 1 LF RESET $end
$upscope $end
$upscope $end

$scope module FTB_61__60 $end
$var wire 1 {% X $end
$var wire 1 B% A $end
$var supply1 1 MF VPWR $end
$var supply0 1 NF VGND $end
$var supply1 1 OF VPB $end
$var supply0 1 PF VNB $end

$scope module base $end
$var wire 1 {% X $end
$var wire 1 B% A $end
$var wire 1 QF buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_35 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 {% ccff_head [0] $end
$var wire 1 |% ccff_tail [0] $end
$var wire 1 C% mem_out [0] $end
$var wire 1 D% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 C% Q $end
$var wire 1 }$ CLK $end
$var wire 1 {% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 RF VPWR $end
$var supply0 1 SF VGND $end
$var supply1 1 TF VPB $end
$var supply0 1 UF VNB $end

$scope module base $end
$var wire 1 C% Q $end
$var wire 1 }$ CLK $end
$var wire 1 {% D $end
$var wire 1 K# RESET_B $end
$var wire 1 VF buf_Q $end
$var wire 1 WF RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 D% Q $end
$var wire 1 }$ CLK $end
$var wire 1 C% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 XF VPWR $end
$var supply0 1 YF VGND $end
$var supply1 1 ZF VPB $end
$var supply0 1 [F VNB $end

$scope module base $end
$var wire 1 D% Q $end
$var wire 1 }$ CLK $end
$var wire 1 C% D $end
$var wire 1 K# RESET_B $end
$var wire 1 \F buf_Q $end
$var wire 1 ]F RESET $end
$upscope $end
$upscope $end

$scope module FTB_62__61 $end
$var wire 1 |% X $end
$var wire 1 D% A $end
$var supply1 1 ^F VPWR $end
$var supply0 1 _F VGND $end
$var supply1 1 `F VPB $end
$var supply0 1 aF VNB $end

$scope module base $end
$var wire 1 |% X $end
$var wire 1 D% A $end
$var wire 1 bF buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_37 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 |% ccff_head [0] $end
$var wire 1 }% ccff_tail [0] $end
$var wire 1 E% mem_out [0] $end
$var wire 1 F% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 E% Q $end
$var wire 1 }$ CLK $end
$var wire 1 |% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 cF VPWR $end
$var supply0 1 dF VGND $end
$var supply1 1 eF VPB $end
$var supply0 1 fF VNB $end

$scope module base $end
$var wire 1 E% Q $end
$var wire 1 }$ CLK $end
$var wire 1 |% D $end
$var wire 1 K# RESET_B $end
$var wire 1 gF buf_Q $end
$var wire 1 hF RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 F% Q $end
$var wire 1 }$ CLK $end
$var wire 1 E% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 iF VPWR $end
$var supply0 1 jF VGND $end
$var supply1 1 kF VPB $end
$var supply0 1 lF VNB $end

$scope module base $end
$var wire 1 F% Q $end
$var wire 1 }$ CLK $end
$var wire 1 E% D $end
$var wire 1 K# RESET_B $end
$var wire 1 mF buf_Q $end
$var wire 1 nF RESET $end
$upscope $end
$upscope $end

$scope module FTB_63__62 $end
$var wire 1 }% X $end
$var wire 1 F% A $end
$var supply1 1 oF VPWR $end
$var supply0 1 pF VGND $end
$var supply1 1 qF VPB $end
$var supply0 1 rF VNB $end

$scope module base $end
$var wire 1 }% X $end
$var wire 1 F% A $end
$var wire 1 sF buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_39 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 }% ccff_head [0] $end
$var wire 1 ~% ccff_tail [0] $end
$var wire 1 G% mem_out [0] $end
$var wire 1 H% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 G% Q $end
$var wire 1 }$ CLK $end
$var wire 1 }% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 tF VPWR $end
$var supply0 1 uF VGND $end
$var supply1 1 vF VPB $end
$var supply0 1 wF VNB $end

$scope module base $end
$var wire 1 G% Q $end
$var wire 1 }$ CLK $end
$var wire 1 }% D $end
$var wire 1 K# RESET_B $end
$var wire 1 xF buf_Q $end
$var wire 1 yF RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 H% Q $end
$var wire 1 }$ CLK $end
$var wire 1 G% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 zF VPWR $end
$var supply0 1 {F VGND $end
$var supply1 1 |F VPB $end
$var supply0 1 }F VNB $end

$scope module base $end
$var wire 1 H% Q $end
$var wire 1 }$ CLK $end
$var wire 1 G% D $end
$var wire 1 K# RESET_B $end
$var wire 1 ~F buf_Q $end
$var wire 1 !G RESET $end
$upscope $end
$upscope $end

$scope module FTB_64__63 $end
$var wire 1 ~% X $end
$var wire 1 H% A $end
$var supply1 1 "G VPWR $end
$var supply0 1 #G VGND $end
$var supply1 1 $G VPB $end
$var supply0 1 %G VNB $end

$scope module base $end
$var wire 1 ~% X $end
$var wire 1 H% A $end
$var wire 1 &G buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_41 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 ~% ccff_head [0] $end
$var wire 1 !& ccff_tail [0] $end
$var wire 1 I% mem_out [0] $end
$var wire 1 J% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 I% Q $end
$var wire 1 }$ CLK $end
$var wire 1 ~% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 'G VPWR $end
$var supply0 1 (G VGND $end
$var supply1 1 )G VPB $end
$var supply0 1 *G VNB $end

$scope module base $end
$var wire 1 I% Q $end
$var wire 1 }$ CLK $end
$var wire 1 ~% D $end
$var wire 1 K# RESET_B $end
$var wire 1 +G buf_Q $end
$var wire 1 ,G RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 J% Q $end
$var wire 1 }$ CLK $end
$var wire 1 I% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 -G VPWR $end
$var supply0 1 .G VGND $end
$var supply1 1 /G VPB $end
$var supply0 1 0G VNB $end

$scope module base $end
$var wire 1 J% Q $end
$var wire 1 }$ CLK $end
$var wire 1 I% D $end
$var wire 1 K# RESET_B $end
$var wire 1 1G buf_Q $end
$var wire 1 2G RESET $end
$upscope $end
$upscope $end

$scope module FTB_65__64 $end
$var wire 1 !& X $end
$var wire 1 J% A $end
$var supply1 1 3G VPWR $end
$var supply0 1 4G VGND $end
$var supply1 1 5G VPB $end
$var supply0 1 6G VNB $end

$scope module base $end
$var wire 1 !& X $end
$var wire 1 J% A $end
$var wire 1 7G buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_43 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 !& ccff_head [0] $end
$var wire 1 "& ccff_tail [0] $end
$var wire 1 K% mem_out [0] $end
$var wire 1 L% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 K% Q $end
$var wire 1 }$ CLK $end
$var wire 1 !& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 8G VPWR $end
$var supply0 1 9G VGND $end
$var supply1 1 :G VPB $end
$var supply0 1 ;G VNB $end

$scope module base $end
$var wire 1 K% Q $end
$var wire 1 }$ CLK $end
$var wire 1 !& D $end
$var wire 1 K# RESET_B $end
$var wire 1 <G buf_Q $end
$var wire 1 =G RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 L% Q $end
$var wire 1 }$ CLK $end
$var wire 1 K% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 >G VPWR $end
$var supply0 1 ?G VGND $end
$var supply1 1 @G VPB $end
$var supply0 1 AG VNB $end

$scope module base $end
$var wire 1 L% Q $end
$var wire 1 }$ CLK $end
$var wire 1 K% D $end
$var wire 1 K# RESET_B $end
$var wire 1 BG buf_Q $end
$var wire 1 CG RESET $end
$upscope $end
$upscope $end

$scope module FTB_66__65 $end
$var wire 1 "& X $end
$var wire 1 L% A $end
$var supply1 1 DG VPWR $end
$var supply0 1 EG VGND $end
$var supply1 1 FG VPB $end
$var supply0 1 GG VNB $end

$scope module base $end
$var wire 1 "& X $end
$var wire 1 L% A $end
$var wire 1 HG buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_45 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 "& ccff_head [0] $end
$var wire 1 $& ccff_tail [0] $end
$var wire 1 O% mem_out [0] $end
$var wire 1 P% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 O% Q $end
$var wire 1 }$ CLK $end
$var wire 1 "& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 IG VPWR $end
$var supply0 1 JG VGND $end
$var supply1 1 KG VPB $end
$var supply0 1 LG VNB $end

$scope module base $end
$var wire 1 O% Q $end
$var wire 1 }$ CLK $end
$var wire 1 "& D $end
$var wire 1 K# RESET_B $end
$var wire 1 MG buf_Q $end
$var wire 1 NG RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 P% Q $end
$var wire 1 }$ CLK $end
$var wire 1 O% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 OG VPWR $end
$var supply0 1 PG VGND $end
$var supply1 1 QG VPB $end
$var supply0 1 RG VNB $end

$scope module base $end
$var wire 1 P% Q $end
$var wire 1 }$ CLK $end
$var wire 1 O% D $end
$var wire 1 K# RESET_B $end
$var wire 1 SG buf_Q $end
$var wire 1 TG RESET $end
$upscope $end
$upscope $end

$scope module FTB_67__66 $end
$var wire 1 $& X $end
$var wire 1 P% A $end
$var supply1 1 UG VPWR $end
$var supply0 1 VG VGND $end
$var supply1 1 WG VPB $end
$var supply0 1 XG VNB $end

$scope module base $end
$var wire 1 $& X $end
$var wire 1 P% A $end
$var wire 1 YG buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_47 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 $& ccff_head [0] $end
$var wire 1 %& ccff_tail [0] $end
$var wire 1 Q% mem_out [0] $end
$var wire 1 R% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 Q% Q $end
$var wire 1 }$ CLK $end
$var wire 1 $& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 ZG VPWR $end
$var supply0 1 [G VGND $end
$var supply1 1 \G VPB $end
$var supply0 1 ]G VNB $end

$scope module base $end
$var wire 1 Q% Q $end
$var wire 1 }$ CLK $end
$var wire 1 $& D $end
$var wire 1 K# RESET_B $end
$var wire 1 ^G buf_Q $end
$var wire 1 _G RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 R% Q $end
$var wire 1 }$ CLK $end
$var wire 1 Q% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 `G VPWR $end
$var supply0 1 aG VGND $end
$var supply1 1 bG VPB $end
$var supply0 1 cG VNB $end

$scope module base $end
$var wire 1 R% Q $end
$var wire 1 }$ CLK $end
$var wire 1 Q% D $end
$var wire 1 K# RESET_B $end
$var wire 1 dG buf_Q $end
$var wire 1 eG RESET $end
$upscope $end
$upscope $end

$scope module FTB_68__67 $end
$var wire 1 %& X $end
$var wire 1 R% A $end
$var supply1 1 fG VPWR $end
$var supply0 1 gG VGND $end
$var supply1 1 hG VPB $end
$var supply0 1 iG VNB $end

$scope module base $end
$var wire 1 %& X $end
$var wire 1 R% A $end
$var wire 1 jG buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_49 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 %& ccff_head [0] $end
$var wire 1 && ccff_tail [0] $end
$var wire 1 S% mem_out [0] $end
$var wire 1 T% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 S% Q $end
$var wire 1 }$ CLK $end
$var wire 1 %& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 kG VPWR $end
$var supply0 1 lG VGND $end
$var supply1 1 mG VPB $end
$var supply0 1 nG VNB $end

$scope module base $end
$var wire 1 S% Q $end
$var wire 1 }$ CLK $end
$var wire 1 %& D $end
$var wire 1 K# RESET_B $end
$var wire 1 oG buf_Q $end
$var wire 1 pG RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 T% Q $end
$var wire 1 }$ CLK $end
$var wire 1 S% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 qG VPWR $end
$var supply0 1 rG VGND $end
$var supply1 1 sG VPB $end
$var supply0 1 tG VNB $end

$scope module base $end
$var wire 1 T% Q $end
$var wire 1 }$ CLK $end
$var wire 1 S% D $end
$var wire 1 K# RESET_B $end
$var wire 1 uG buf_Q $end
$var wire 1 vG RESET $end
$upscope $end
$upscope $end

$scope module FTB_69__68 $end
$var wire 1 && X $end
$var wire 1 T% A $end
$var supply1 1 wG VPWR $end
$var supply0 1 xG VGND $end
$var supply1 1 yG VPB $end
$var supply0 1 zG VNB $end

$scope module base $end
$var wire 1 && X $end
$var wire 1 T% A $end
$var wire 1 {G buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_51 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 && ccff_head [0] $end
$var wire 1 '& ccff_tail [0] $end
$var wire 1 U% mem_out [0] $end
$var wire 1 V% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 U% Q $end
$var wire 1 }$ CLK $end
$var wire 1 && D $end
$var wire 1 K# RESET_B $end
$var supply1 1 |G VPWR $end
$var supply0 1 }G VGND $end
$var supply1 1 ~G VPB $end
$var supply0 1 !H VNB $end

$scope module base $end
$var wire 1 U% Q $end
$var wire 1 }$ CLK $end
$var wire 1 && D $end
$var wire 1 K# RESET_B $end
$var wire 1 "H buf_Q $end
$var wire 1 #H RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 V% Q $end
$var wire 1 }$ CLK $end
$var wire 1 U% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 $H VPWR $end
$var supply0 1 %H VGND $end
$var supply1 1 &H VPB $end
$var supply0 1 'H VNB $end

$scope module base $end
$var wire 1 V% Q $end
$var wire 1 }$ CLK $end
$var wire 1 U% D $end
$var wire 1 K# RESET_B $end
$var wire 1 (H buf_Q $end
$var wire 1 )H RESET $end
$upscope $end
$upscope $end

$scope module FTB_70__69 $end
$var wire 1 '& X $end
$var wire 1 V% A $end
$var supply1 1 *H VPWR $end
$var supply0 1 +H VGND $end
$var supply1 1 ,H VPB $end
$var supply0 1 -H VNB $end

$scope module base $end
$var wire 1 '& X $end
$var wire 1 V% A $end
$var wire 1 .H buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_55 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 <& ccff_head [0] $end
$var wire 1 (& ccff_tail [0] $end
$var wire 1 W% mem_out [0] $end
$var wire 1 X% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 W% Q $end
$var wire 1 }$ CLK $end
$var wire 1 <& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 /H VPWR $end
$var supply0 1 0H VGND $end
$var supply1 1 1H VPB $end
$var supply0 1 2H VNB $end

$scope module base $end
$var wire 1 W% Q $end
$var wire 1 }$ CLK $end
$var wire 1 <& D $end
$var wire 1 K# RESET_B $end
$var wire 1 3H buf_Q $end
$var wire 1 4H RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 X% Q $end
$var wire 1 }$ CLK $end
$var wire 1 W% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 5H VPWR $end
$var supply0 1 6H VGND $end
$var supply1 1 7H VPB $end
$var supply0 1 8H VNB $end

$scope module base $end
$var wire 1 X% Q $end
$var wire 1 }$ CLK $end
$var wire 1 W% D $end
$var wire 1 K# RESET_B $end
$var wire 1 9H buf_Q $end
$var wire 1 :H RESET $end
$upscope $end
$upscope $end

$scope module FTB_71__70 $end
$var wire 1 (& X $end
$var wire 1 X% A $end
$var supply1 1 ;H VPWR $end
$var supply0 1 <H VGND $end
$var supply1 1 =H VPB $end
$var supply0 1 >H VNB $end

$scope module base $end
$var wire 1 (& X $end
$var wire 1 X% A $end
$var wire 1 ?H buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_57 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 (& ccff_head [0] $end
$var wire 1 )& ccff_tail [0] $end
$var wire 1 Y% mem_out [0] $end
$var wire 1 Z% mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 Y% Q $end
$var wire 1 }$ CLK $end
$var wire 1 (& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 @H VPWR $end
$var supply0 1 AH VGND $end
$var supply1 1 BH VPB $end
$var supply0 1 CH VNB $end

$scope module base $end
$var wire 1 Y% Q $end
$var wire 1 }$ CLK $end
$var wire 1 (& D $end
$var wire 1 K# RESET_B $end
$var wire 1 DH buf_Q $end
$var wire 1 EH RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 Z% Q $end
$var wire 1 }$ CLK $end
$var wire 1 Y% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 FH VPWR $end
$var supply0 1 GH VGND $end
$var supply1 1 HH VPB $end
$var supply0 1 IH VNB $end

$scope module base $end
$var wire 1 Z% Q $end
$var wire 1 }$ CLK $end
$var wire 1 Y% D $end
$var wire 1 K# RESET_B $end
$var wire 1 JH buf_Q $end
$var wire 1 KH RESET $end
$upscope $end
$upscope $end

$scope module FTB_72__71 $end
$var wire 1 )& X $end
$var wire 1 Z% A $end
$var supply1 1 LH VPWR $end
$var supply0 1 MH VGND $end
$var supply1 1 NH VPB $end
$var supply0 1 OH VNB $end

$scope module base $end
$var wire 1 )& X $end
$var wire 1 Z% A $end
$var wire 1 PH buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_59 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 )& ccff_head [0] $end
$var wire 1 y$ ccff_tail [0] $end
$var wire 1 [% mem_out [0] $end
$var wire 1 \% mem_out [1] $end
$var wire 1 QH copt_net_180 $end
$var wire 1 RH copt_net_182 $end
$var wire 1 SH copt_net_181 $end
$var wire 1 TH copt_net_185 $end
$var wire 1 UH copt_net_184 $end
$var wire 1 VH copt_net_183 $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 [% Q $end
$var wire 1 }$ CLK $end
$var wire 1 )& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 WH VPWR $end
$var supply0 1 XH VGND $end
$var supply1 1 YH VPB $end
$var supply0 1 ZH VNB $end

$scope module base $end
$var wire 1 [% Q $end
$var wire 1 }$ CLK $end
$var wire 1 )& D $end
$var wire 1 K# RESET_B $end
$var wire 1 [H buf_Q $end
$var wire 1 \H RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 QH Q $end
$var wire 1 }$ CLK $end
$var wire 1 [% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 ]H VPWR $end
$var supply0 1 ^H VGND $end
$var supply1 1 _H VPB $end
$var supply0 1 `H VNB $end

$scope module base $end
$var wire 1 QH Q $end
$var wire 1 }$ CLK $end
$var wire 1 [% D $end
$var wire 1 K# RESET_B $end
$var wire 1 aH buf_Q $end
$var wire 1 bH RESET $end
$upscope $end
$upscope $end

$scope module FTB_73__72 $end
$var wire 1 y$ X $end
$var wire 1 \% A $end
$var supply1 1 cH VPWR $end
$var supply0 1 dH VGND $end
$var supply1 1 eH VPB $end
$var supply0 1 fH VNB $end

$scope module base $end
$var wire 1 y$ X $end
$var wire 1 \% A $end
$var wire 1 gH buf0_out_X $end
$upscope $end
$upscope $end

$scope module copt_h_inst_1376 $end
$var wire 1 \% X $end
$var wire 1 RH A $end
$var supply1 1 hH VPWR $end
$var supply0 1 iH VGND $end
$var supply1 1 jH VPB $end
$var supply0 1 kH VNB $end

$scope module base $end
$var wire 1 \% X $end
$var wire 1 RH A $end
$var wire 1 lH buf0_out_X $end
$upscope $end
$upscope $end

$scope module copt_h_inst_1377 $end
$var wire 1 SH X $end
$var wire 1 QH A $end
$var supply1 1 mH VPWR $end
$var supply0 1 nH VGND $end
$var supply1 1 oH VPB $end
$var supply0 1 pH VNB $end

$scope module base $end
$var wire 1 SH X $end
$var wire 1 QH A $end
$var wire 1 qH buf0_out_X $end
$upscope $end
$upscope $end

$scope module copt_h_inst_1378 $end
$var wire 1 RH X $end
$var wire 1 TH A $end
$var supply1 1 rH VPWR $end
$var supply0 1 sH VGND $end
$var supply1 1 tH VPB $end
$var supply0 1 uH VNB $end

$scope module base $end
$var wire 1 RH X $end
$var wire 1 TH A $end
$var wire 1 vH buf0_out_X $end
$upscope $end
$upscope $end

$scope module copt_h_inst_1379 $end
$var wire 1 VH X $end
$var wire 1 UH A $end
$var supply1 1 wH VPWR $end
$var supply0 1 xH VGND $end
$var supply1 1 yH VPB $end
$var supply0 1 zH VNB $end

$scope module base $end
$var wire 1 VH X $end
$var wire 1 UH A $end
$var wire 1 {H buf0_out_X $end
$upscope $end
$upscope $end

$scope module copt_h_inst_1380 $end
$var wire 1 UH X $end
$var wire 1 SH A $end
$var supply1 1 |H VPWR $end
$var supply0 1 }H VGND $end
$var supply1 1 ~H VPB $end
$var supply0 1 !I VNB $end

$scope module base $end
$var wire 1 UH X $end
$var wire 1 SH A $end
$var wire 1 "I buf0_out_X $end
$upscope $end
$upscope $end

$scope module copt_h_inst_1381 $end
$var wire 1 TH X $end
$var wire 1 VH A $end
$var supply1 1 #I VPWR $end
$var supply0 1 $I VGND $end
$var supply1 1 %I VPB $end
$var supply0 1 &I VNB $end

$scope module base $end
$var wire 1 TH X $end
$var wire 1 VH A $end
$var wire 1 'I buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_29 $end
$var wire 1 j# in [0] $end
$var wire 1 r# in [1] $end
$var wire 1 $$ in [2] $end
$var wire 1 1& sram [0] $end
$var wire 1 2& sram [1] $end
$var wire 1 =( sram_inv [0] $end
$var wire 1 >( sram_inv [1] $end
$var wire 1 K$ out [0] $end
$var wire 1 1' p0 $end
$var wire 1 (I mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 )I mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 *I mux_2level_tapbuf_basis_input2_mem1_2_out [0] $end
$var wire 1 +I SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 ,I SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 -I SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 .I SYNOPSYS_UNCONNECTED_4 $end
$var wire 1 /I BUF_net_171 $end

$scope module mux_l1_in_0_ $end
$var wire 1 j# in [0] $end
$var wire 1 r# in [1] $end
$var wire 1 1& mem [0] $end
$var wire 1 +I mem_inv [0] $end
$var wire 1 (I out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 (I X $end
$var wire 1 r# A0 $end
$var wire 1 j# A1 $end
$var wire 1 1& S $end
$var supply1 1 0I VPWR $end
$var supply0 1 1I VGND $end
$var supply1 1 2I VPB $end
$var supply0 1 3I VNB $end

$scope module base $end
$var wire 1 (I X $end
$var wire 1 r# A0 $end
$var wire 1 j# A1 $end
$var wire 1 1& S $end
$var wire 1 4I mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l1_in_1_ $end
$var wire 1 $$ in [0] $end
$var wire 1 ,I in [1] $end
$var wire 1 1& mem [0] $end
$var wire 1 -I mem_inv [0] $end
$var wire 1 )I out [0] $end
$var wire 1 1' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 )I X $end
$var wire 1 1' A0 $end
$var wire 1 $$ A1 $end
$var wire 1 1& S $end
$var supply1 1 5I VPWR $end
$var supply0 1 6I VGND $end
$var supply1 1 7I VPB $end
$var supply0 1 8I VNB $end

$scope module base $end
$var wire 1 )I X $end
$var wire 1 1' A0 $end
$var wire 1 $$ A1 $end
$var wire 1 1& S $end
$var wire 1 9I mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 (I in [0] $end
$var wire 1 )I in [1] $end
$var wire 1 2& mem [0] $end
$var wire 1 .I mem_inv [0] $end
$var wire 1 *I out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 *I X $end
$var wire 1 )I A0 $end
$var wire 1 (I A1 $end
$var wire 1 2& S $end
$var supply1 1 :I VPWR $end
$var supply0 1 ;I VGND $end
$var supply1 1 <I VPB $end
$var supply0 1 =I VNB $end

$scope module base $end
$var wire 1 *I X $end
$var wire 1 )I A0 $end
$var wire 1 (I A1 $end
$var wire 1 2& S $end
$var wire 1 >I mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_170 $end
$var wire 1 K$ Y $end
$var wire 1 /I A $end
$var supply1 1 ?I VPWR $end
$var supply0 1 @I VGND $end
$var supply1 1 AI VPB $end
$var supply0 1 BI VNB $end

$scope module base $end
$var wire 1 K$ Y $end
$var wire 1 /I A $end
$var wire 1 CI not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_171 $end
$var wire 1 /I Y $end
$var wire 1 *I A $end
$var supply1 1 DI VPWR $end
$var supply0 1 EI VGND $end
$var supply1 1 FI VPB $end
$var supply0 1 GI VNB $end

$scope module base $end
$var wire 1 /I Y $end
$var wire 1 *I A $end
$var wire 1 HI not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_bottom_track_45 $end
$var wire 1 j# in [0] $end
$var wire 1 n# in [1] $end
$var wire 1 ,$ in [2] $end
$var wire 1 3& sram [0] $end
$var wire 1 4& sram [1] $end
$var wire 1 ?( sram_inv [0] $end
$var wire 1 @( sram_inv [1] $end
$var wire 1 S$ out [0] $end
$var wire 1 R' p0 $end
$var wire 1 II mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 JI mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 KI mux_2level_tapbuf_basis_input2_mem1_2_out [0] $end
$var wire 1 LI SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 MI SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 NI SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 OI SYNOPSYS_UNCONNECTED_4 $end

$scope module sky130_fd_sc_hd__buf_4_0_ $end
$var wire 1 S$ X $end
$var wire 1 KI A $end
$var supply1 1 PI VPWR $end
$var supply0 1 QI VGND $end
$var supply1 1 RI VPB $end
$var supply0 1 SI VNB $end

$scope module base $end
$var wire 1 S$ X $end
$var wire 1 KI A $end
$var wire 1 TI buf0_out_X $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 j# in [0] $end
$var wire 1 n# in [1] $end
$var wire 1 3& mem [0] $end
$var wire 1 LI mem_inv [0] $end
$var wire 1 II out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 II X $end
$var wire 1 n# A0 $end
$var wire 1 j# A1 $end
$var wire 1 3& S $end
$var supply1 1 UI VPWR $end
$var supply0 1 VI VGND $end
$var supply1 1 WI VPB $end
$var supply0 1 XI VNB $end

$scope module base $end
$var wire 1 II X $end
$var wire 1 n# A0 $end
$var wire 1 j# A1 $end
$var wire 1 3& S $end
$var wire 1 YI mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l1_in_1_ $end
$var wire 1 ,$ in [0] $end
$var wire 1 MI in [1] $end
$var wire 1 3& mem [0] $end
$var wire 1 NI mem_inv [0] $end
$var wire 1 JI out [0] $end
$var wire 1 R' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 JI X $end
$var wire 1 R' A0 $end
$var wire 1 ,$ A1 $end
$var wire 1 3& S $end
$var supply1 1 ZI VPWR $end
$var supply0 1 [I VGND $end
$var supply1 1 \I VPB $end
$var supply0 1 ]I VNB $end

$scope module base $end
$var wire 1 JI X $end
$var wire 1 R' A0 $end
$var wire 1 ,$ A1 $end
$var wire 1 3& S $end
$var wire 1 ^I mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 II in [0] $end
$var wire 1 JI in [1] $end
$var wire 1 4& mem [0] $end
$var wire 1 OI mem_inv [0] $end
$var wire 1 KI out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 KI X $end
$var wire 1 JI A0 $end
$var wire 1 II A1 $end
$var wire 1 4& S $end
$var supply1 1 _I VPWR $end
$var supply0 1 `I VGND $end
$var supply1 1 aI VPB $end
$var supply0 1 bI VNB $end

$scope module base $end
$var wire 1 KI X $end
$var wire 1 JI A0 $end
$var wire 1 II A1 $end
$var wire 1 4& S $end
$var wire 1 cI mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_29 $end
$var wire 1 Y# in [0] $end
$var wire 1 3$ in [1] $end
$var wire 1 ;$ in [2] $end
$var wire 1 5& sram [0] $end
$var wire 1 6& sram [1] $end
$var wire 1 A( sram_inv [0] $end
$var wire 1 B( sram_inv [1] $end
$var wire 1 i$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 dI mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 eI mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 fI mux_2level_tapbuf_basis_input2_mem1_2_out [0] $end
$var wire 1 gI SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 hI SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 iI SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 jI SYNOPSYS_UNCONNECTED_4 $end
$var wire 1 kI BUF_net_173 $end

$scope module mux_l1_in_0_ $end
$var wire 1 Y# in [0] $end
$var wire 1 3$ in [1] $end
$var wire 1 5& mem [0] $end
$var wire 1 gI mem_inv [0] $end
$var wire 1 dI out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 dI X $end
$var wire 1 3$ A0 $end
$var wire 1 Y# A1 $end
$var wire 1 5& S $end
$var supply1 1 lI VPWR $end
$var supply0 1 mI VGND $end
$var supply1 1 nI VPB $end
$var supply0 1 oI VNB $end

$scope module base $end
$var wire 1 dI X $end
$var wire 1 3$ A0 $end
$var wire 1 Y# A1 $end
$var wire 1 5& S $end
$var wire 1 pI mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l1_in_1_ $end
$var wire 1 ;$ in [0] $end
$var wire 1 hI in [1] $end
$var wire 1 5& mem [0] $end
$var wire 1 iI mem_inv [0] $end
$var wire 1 eI out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 eI X $end
$var wire 1 p' A0 $end
$var wire 1 ;$ A1 $end
$var wire 1 5& S $end
$var supply1 1 qI VPWR $end
$var supply0 1 rI VGND $end
$var supply1 1 sI VPB $end
$var supply0 1 tI VNB $end

$scope module base $end
$var wire 1 eI X $end
$var wire 1 p' A0 $end
$var wire 1 ;$ A1 $end
$var wire 1 5& S $end
$var wire 1 uI mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 dI in [0] $end
$var wire 1 eI in [1] $end
$var wire 1 6& mem [0] $end
$var wire 1 jI mem_inv [0] $end
$var wire 1 fI out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 fI X $end
$var wire 1 eI A0 $end
$var wire 1 dI A1 $end
$var wire 1 6& S $end
$var supply1 1 vI VPWR $end
$var supply0 1 wI VGND $end
$var supply1 1 xI VPB $end
$var supply0 1 yI VNB $end

$scope module base $end
$var wire 1 fI X $end
$var wire 1 eI A0 $end
$var wire 1 dI A1 $end
$var wire 1 6& S $end
$var wire 1 zI mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module BINV_R_172 $end
$var wire 1 i$ Y $end
$var wire 1 kI A $end
$var supply1 1 {I VPWR $end
$var supply0 1 |I VGND $end
$var supply1 1 }I VPB $end
$var supply0 1 ~I VNB $end

$scope module base $end
$var wire 1 i$ Y $end
$var wire 1 kI A $end
$var wire 1 !J not0_out_Y $end
$upscope $end
$upscope $end

$scope module BINV_R_173 $end
$var wire 1 kI Y $end
$var wire 1 fI A $end
$var supply1 1 "J VPWR $end
$var supply0 1 #J VGND $end
$var supply1 1 $J VPB $end
$var supply0 1 %J VNB $end

$scope module base $end
$var wire 1 kI Y $end
$var wire 1 fI A $end
$var wire 1 &J not0_out_Y $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_left_track_53 $end
$var wire 1 e# in [0] $end
$var wire 1 7$ in [1] $end
$var wire 1 ;$ in [2] $end
$var wire 1 7& sram [0] $end
$var wire 1 8& sram [1] $end
$var wire 1 C( sram_inv [0] $end
$var wire 1 D( sram_inv [1] $end
$var wire 1 u$ out [0] $end
$var wire 1 p' p0 $end
$var wire 1 'J mux_2level_tapbuf_basis_input2_mem1_0_out [0] $end
$var wire 1 (J mux_2level_tapbuf_basis_input2_mem1_1_out [0] $end
$var wire 1 )J mux_2level_tapbuf_basis_input2_mem1_2_out [0] $end
$var wire 1 *J SYNOPSYS_UNCONNECTED_1 $end
$var wire 1 +J SYNOPSYS_UNCONNECTED_2 $end
$var wire 1 ,J SYNOPSYS_UNCONNECTED_3 $end
$var wire 1 -J SYNOPSYS_UNCONNECTED_4 $end

$scope module sky130_fd_sc_hd__buf_4_0_ $end
$var wire 1 u$ X $end
$var wire 1 )J A $end
$var supply1 1 .J VPWR $end
$var supply0 1 /J VGND $end
$var supply1 1 0J VPB $end
$var supply0 1 1J VNB $end

$scope module base $end
$var wire 1 u$ X $end
$var wire 1 )J A $end
$var wire 1 2J buf0_out_X $end
$upscope $end
$upscope $end

$scope module mux_l1_in_0_ $end
$var wire 1 e# in [0] $end
$var wire 1 7$ in [1] $end
$var wire 1 7& mem [0] $end
$var wire 1 *J mem_inv [0] $end
$var wire 1 'J out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 'J X $end
$var wire 1 7$ A0 $end
$var wire 1 e# A1 $end
$var wire 1 7& S $end
$var supply1 1 3J VPWR $end
$var supply0 1 4J VGND $end
$var supply1 1 5J VPB $end
$var supply0 1 6J VNB $end

$scope module base $end
$var wire 1 'J X $end
$var wire 1 7$ A0 $end
$var wire 1 e# A1 $end
$var wire 1 7& S $end
$var wire 1 7J mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l1_in_1_ $end
$var wire 1 ;$ in [0] $end
$var wire 1 +J in [1] $end
$var wire 1 7& mem [0] $end
$var wire 1 ,J mem_inv [0] $end
$var wire 1 (J out [0] $end
$var wire 1 p' p0 $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 (J X $end
$var wire 1 p' A0 $end
$var wire 1 ;$ A1 $end
$var wire 1 7& S $end
$var supply1 1 8J VPWR $end
$var supply0 1 9J VGND $end
$var supply1 1 :J VPB $end
$var supply0 1 ;J VNB $end

$scope module base $end
$var wire 1 (J X $end
$var wire 1 p' A0 $end
$var wire 1 ;$ A1 $end
$var wire 1 7& S $end
$var wire 1 <J mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mux_l2_in_0_ $end
$var wire 1 'J in [0] $end
$var wire 1 (J in [1] $end
$var wire 1 8& mem [0] $end
$var wire 1 -J mem_inv [0] $end
$var wire 1 )J out [0] $end

$scope module sky130_fd_sc_hd__mux2_1_0 $end
$var wire 1 )J X $end
$var wire 1 (J A0 $end
$var wire 1 'J A1 $end
$var wire 1 8& S $end
$var supply1 1 =J VPWR $end
$var supply0 1 >J VGND $end
$var supply1 1 ?J VPB $end
$var supply0 1 @J VNB $end

$scope module base $end
$var wire 1 )J X $end
$var wire 1 (J A0 $end
$var wire 1 'J A1 $end
$var wire 1 8& S $end
$var wire 1 AJ mux_2to10_out_X $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_29 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 .& ccff_head [0] $end
$var wire 1 9& ccff_tail [0] $end
$var wire 1 1& mem_out [0] $end
$var wire 1 2& mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 1& Q $end
$var wire 1 }$ CLK $end
$var wire 1 .& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 BJ VPWR $end
$var supply0 1 CJ VGND $end
$var supply1 1 DJ VPB $end
$var supply0 1 EJ VNB $end

$scope module base $end
$var wire 1 1& Q $end
$var wire 1 }$ CLK $end
$var wire 1 .& D $end
$var wire 1 K# RESET_B $end
$var wire 1 FJ buf_Q $end
$var wire 1 GJ RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 2& Q $end
$var wire 1 }$ CLK $end
$var wire 1 1& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 HJ VPWR $end
$var supply0 1 IJ VGND $end
$var supply1 1 JJ VPB $end
$var supply0 1 KJ VNB $end

$scope module base $end
$var wire 1 2& Q $end
$var wire 1 }$ CLK $end
$var wire 1 1& D $end
$var wire 1 K# RESET_B $end
$var wire 1 LJ buf_Q $end
$var wire 1 MJ RESET $end
$upscope $end
$upscope $end

$scope module FTB_74__73 $end
$var wire 1 9& X $end
$var wire 1 2& A $end
$var supply1 1 NJ VPWR $end
$var supply0 1 OJ VGND $end
$var supply1 1 PJ VPB $end
$var supply0 1 QJ VNB $end

$scope module base $end
$var wire 1 9& X $end
$var wire 1 2& A $end
$var wire 1 RJ buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_bottom_track_45 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 l% ccff_head [0] $end
$var wire 1 :& ccff_tail [0] $end
$var wire 1 3& mem_out [0] $end
$var wire 1 4& mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 3& Q $end
$var wire 1 }$ CLK $end
$var wire 1 l% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 SJ VPWR $end
$var supply0 1 TJ VGND $end
$var supply1 1 UJ VPB $end
$var supply0 1 VJ VNB $end

$scope module base $end
$var wire 1 3& Q $end
$var wire 1 }$ CLK $end
$var wire 1 l% D $end
$var wire 1 K# RESET_B $end
$var wire 1 WJ buf_Q $end
$var wire 1 XJ RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 4& Q $end
$var wire 1 }$ CLK $end
$var wire 1 3& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 YJ VPWR $end
$var supply0 1 ZJ VGND $end
$var supply1 1 [J VPB $end
$var supply0 1 \J VNB $end

$scope module base $end
$var wire 1 4& Q $end
$var wire 1 }$ CLK $end
$var wire 1 3& D $end
$var wire 1 K# RESET_B $end
$var wire 1 ]J buf_Q $end
$var wire 1 ^J RESET $end
$upscope $end
$upscope $end

$scope module FTB_75__74 $end
$var wire 1 :& X $end
$var wire 1 4& A $end
$var supply1 1 _J VPWR $end
$var supply0 1 `J VGND $end
$var supply1 1 aJ VPB $end
$var supply0 1 bJ VNB $end

$scope module base $end
$var wire 1 :& X $end
$var wire 1 4& A $end
$var wire 1 cJ buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_29 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 y% ccff_head [0] $end
$var wire 1 ;& ccff_tail [0] $end
$var wire 1 5& mem_out [0] $end
$var wire 1 6& mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 5& Q $end
$var wire 1 }$ CLK $end
$var wire 1 y% D $end
$var wire 1 K# RESET_B $end
$var supply1 1 dJ VPWR $end
$var supply0 1 eJ VGND $end
$var supply1 1 fJ VPB $end
$var supply0 1 gJ VNB $end

$scope module base $end
$var wire 1 5& Q $end
$var wire 1 }$ CLK $end
$var wire 1 y% D $end
$var wire 1 K# RESET_B $end
$var wire 1 hJ buf_Q $end
$var wire 1 iJ RESET $end
$upscope $end
$upscope $end

$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
$var wire 1 6& Q $end
$var wire 1 }$ CLK $end
$var wire 1 5& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 jJ VPWR $end
$var supply0 1 kJ VGND $end
$var supply1 1 lJ VPB $end
$var supply0 1 mJ VNB $end

$scope module base $end
$var wire 1 6& Q $end
$var wire 1 }$ CLK $end
$var wire 1 5& D $end
$var wire 1 K# RESET_B $end
$var wire 1 nJ buf_Q $end
$var wire 1 oJ RESET $end
$upscope $end
$upscope $end

$scope module FTB_76__75 $end
$var wire 1 ;& X $end
$var wire 1 6& A $end
$var supply1 1 pJ VPWR $end
$var supply0 1 qJ VGND $end
$var supply1 1 rJ VPB $end
$var supply0 1 sJ VNB $end

$scope module base $end
$var wire 1 ;& X $end
$var wire 1 6& A $end
$var wire 1 tJ buf0_out_X $end
$upscope $end
$upscope $end
$upscope $end

$scope module mem_left_track_53 $end
$var wire 1 K# pReset [0] $end
$var wire 1 }$ prog_clk [0] $end
$var wire 1 '& ccff_head [0] $end
$var wire 1 <& ccff_tail [0] $end
$var wire 1 7& mem_out [0] $end
$var wire 1 8& mem_out [1] $end

$scope module sky130_fd_sc_hd__dfrtp_1_0_ $end
$var wire 1 7& Q $end
$var wire 1 }$ CLK $end
$var wire 1 '& D $end
$var wire 1 K# RESET_B $end
$var supply1 1 uJ VPWR $end
$var supply0 1 vJ VGND $end
$var supply1 1 wJ VPB $end
$var supply0 1 xJ VNB $end

$scope module base $end
$var wire 1 7& Q $end
$var wire 1 }$ CLK $end
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$var wire 1 yJ buf_Q $end
$var wire 1 zJ RESET $end
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$scope module sky130_fd_sc_hd__dfrtp_1_1_ $end
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$var wire 1 }$ CLK $end
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$var wire 1 K# RESET_B $end
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$var supply0 1 |J VGND $end
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$scope module base $end
$var wire 1 8& Q $end
$var wire 1 }$ CLK $end
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$scope module FTB_77__76 $end
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$var wire 1 8& A $end
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$var supply0 1 $K VGND $end
$var supply1 1 %K VPB $end
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$scope module base $end
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$var wire 1 8& A $end
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$upscope $end
$upscope $end

$scope module pReset_FTB00 $end
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$var supply0 1 )K VGND $end
$var supply1 1 *K VPB $end
$var supply0 1 +K VNB $end

$scope module base $end
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$var wire 1 {$ A $end
$var wire 1 ,K buf0_out_X $end
$upscope $end
$upscope $end

$scope module prog_clk_0_FTB00 $end
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$var wire 1 |$ A $end
$var supply1 1 -K VPWR $end
$var supply0 1 .K VGND $end
$var supply1 1 /K VPB $end
$var supply0 1 0K VNB $end

$scope module base $end
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$scope module FTB_78__77 $end
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$var supply0 1 3K VGND $end
$var supply1 1 4K VPB $end
$var supply0 1 5K VNB $end

$scope module base $end
$var wire 1 Z$ X $end
$var wire 1 s# A $end
$var wire 1 6K buf0_out_X $end
$upscope $end
$upscope $end

$scope module FTB_79__78 $end
$var wire 1 L$ X $end
$var wire 1 %$ A $end
$var supply1 1 7K VPWR $end
$var supply0 1 8K VGND $end
$var supply1 1 9K VPB $end
$var supply0 1 :K VNB $end

$scope module base $end
$var wire 1 L$ X $end
$var wire 1 %$ A $end
$var wire 1 ;K buf0_out_X $end
$upscope $end
$upscope $end

$scope module FTB_80__79 $end
$var wire 1 M$ X $end
$var wire 1 &$ A $end
$var supply1 1 <K VPWR $end
$var supply0 1 =K VGND $end
$var supply1 1 >K VPB $end
$var supply0 1 ?K VNB $end

$scope module base $end
$var wire 1 M$ X $end
$var wire 1 &$ A $end
$var wire 1 @K buf0_out_X $end
$upscope $end
$upscope $end

$scope module FTB_81__80 $end
$var wire 1 N$ X $end
$var wire 1 '$ A $end
$var supply1 1 AK VPWR $end
$var supply0 1 BK VGND $end
$var supply1 1 CK VPB $end
$var supply0 1 DK VNB $end

$scope module base $end
$var wire 1 N$ X $end
$var wire 1 '$ A $end
$var wire 1 EK buf0_out_X $end
$upscope $end
$upscope $end

$scope module FTB_82__81 $end
$var wire 1 O$ X $end
$var wire 1 ($ A $end
$var supply1 1 FK VPWR $end
$var supply0 1 GK VGND $end
$var supply1 1 HK VPB $end
$var supply0 1 IK VNB $end

$scope module base $end
$var wire 1 O$ X $end
$var wire 1 ($ A $end
$var wire 1 JK buf0_out_X $end
$upscope $end
$upscope $end

$scope module FTB_83__82 $end
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$var wire 1 1$ A $end
$var supply1 1 KK VPWR $end
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$scope module base $end
$var wire 1 X$ X $end
$var wire 1 1$ A $end
$var wire 1 OK buf0_out_X $end
$upscope $end
$upscope $end

$scope module FTB_84__83 $end
$var wire 1 Y$ X $end
$var wire 1 2$ A $end
$var supply1 1 PK VPWR $end
$var supply0 1 QK VGND $end
$var supply1 1 RK VPB $end
$var supply0 1 SK VNB $end

$scope module base $end
$var wire 1 Y$ X $end
$var wire 1 2$ A $end
$var wire 1 TK buf0_out_X $end
$upscope $end
$upscope $end

$scope module FTB_85__84 $end
$var wire 1 z$ X $end
$var wire 1 $ A $end
$var supply1 1 UK VPWR $end
$var supply0 1 VK VGND $end
$var supply1 1 WK VPB $end
$var supply0 1 XK VNB $end

$scope module base $end
$var wire 1 z$ X $end
$var wire 1 $ A $end
$var wire 1 YK buf0_out_X $end
$upscope $end
$upscope $end

$scope module optlc_176 $end
$var wire 1 (' HI $end
$var wire 1 E( LO $end
$var supply1 1 ZK VPWR $end
$var supply0 1 [K VGND $end
$var supply1 1 \K VPB $end
$var supply0 1 ]K VNB $end

$scope module base $end
$var wire 1 (' HI $end
$var wire 1 E( LO $end
$upscope $end
$upscope $end

$scope module optlc_178 $end
$var wire 1 R' HI $end
$var wire 1 F( LO $end
$var supply1 1 ^K VPWR $end
$var supply0 1 _K VGND $end
$var supply1 1 `K VPB $end
$var supply0 1 aK VNB $end

$scope module base $end
$var wire 1 R' HI $end
$var wire 1 F( LO $end
$upscope $end
$upscope $end

$scope module optlc_181 $end
$var wire 1 p' HI $end
$var wire 1 G( LO $end
$var supply1 1 bK VPWR $end
$var supply0 1 cK VGND $end
$var supply1 1 dK VPB $end
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$scope module base $end
$var wire 1 p' HI $end
$var wire 1 G( LO $end
$upscope $end
$upscope $end

$scope module optlc_184 $end
$var wire 1 1' HI $end
$var wire 1 H( LO $end
$var supply1 1 fK VPWR $end
$var supply0 1 gK VGND $end
$var supply1 1 hK VPB $end
$var supply0 1 iK VNB $end

$scope module base $end
$var wire 1 1' HI $end
$var wire 1 H( LO $end
$upscope $end
$upscope $end

$scope module optlc_186 $end
$var wire 1 }& HI $end
$var wire 1 I( LO $end
$var supply1 1 jK VPWR $end
$var supply0 1 kK VGND $end
$var supply1 1 lK VPB $end
$var supply0 1 mK VNB $end

$scope module base $end
$var wire 1 }& HI $end
$var wire 1 I( LO $end
$upscope $end
$upscope $end

$scope module optlc_188 $end
$var wire 1 Y' HI $end
$var wire 1 J( LO $end
$var supply1 1 nK VPWR $end
$var supply0 1 oK VGND $end
$var supply1 1 pK VPB $end
$var supply0 1 qK VNB $end

$scope module base $end
$var wire 1 Y' HI $end
$var wire 1 J( LO $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
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