# SOFA
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## Introduction

SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework.

This repository provide the following support for the eFPGA IPs
- **Architecture description file** : Users can inspect architecture details and try architecture evalution using the [VTR project](https://github.com/verilog-to-routing/vtr-verilog-to-routing) and the [OpenFPGA project](https://github.com/lnis-uofu/OpenFPGA).
- **Fabrication-ready GDSII layouts**: Users can integrate to their chip designs.
- **Post-layout Verilog Netlists**: Users can run HDL simulations on the eFPGA IPs to validate their applications
- **Benchmark suites**: An example benchmarking suite with which users can run quick examples on the eFPGA IPs
- **Documentation**: Datasheets for each eFPGA IPs downto circuit-level details

<p>
  <img src="./DOC/source/device/hd_fpga/figures/sofa_hd_layout.png" width="200">
  <img src="./DOC/source/device/hd_fpga/figures/qlsofa_hd_layout.png" width="200">
  <img src="./DOC/source/device/hd_fpga/figures/sofa_chd_layout.png" width="200">
</p>

## Quick Start

```bash
#Clone the repository and go inside it
git clone https://github.com/LNIS-Projects/skywater-openfpga.git
python3 SCRIPT/repo_setup.py --openfpga_root_path ${OPENFPGA_PROJECT_DIRECTORY}
```
---

* If you have openfpga repository cloned at the same level of this project, you can simple call
```bash
  python3 SCRIPT/repo_setup.py
``` 

Otherwise, you should provide full path using the option _--openfpga\_root\_path_ 


## Chip Gallery

You can find a chip gallery in the online documentation.

## Directory Organization

* Keep this folder clean and organized as follows
  - **DOC**: documentation of the project
  - **ARCH**: Architecture XML and other input files which OpenFPGA requires to generate Verilog netlists
  - **BENCHMARK**: Benchmarks to be tested on the FPGA fabric
  - **HDL**: Hardware description netlists for the FPGA fabrics
  - **SDC**: design constraints
  - **SCRIPT**: Scripts to setup, run OpenFPGA etc.
  - **TESTBENCH**: Verilog testbenches generated by OpenFPGA 
  - **PDK**: Technology files linked from skywater opensource pdk
  - **SNPS\_ICC2**: workspace of Synopsys IC Compiler 2
                    Keep a README inside the folder about the ICC2 version and how-to-use.
  - **MSIM**: workspace of verification using Mentor ModelSim

---

* Note: 
  - Please **ONLY** place folders under this directory.
    README should be the **ONLY** file under this directory
  - Each EDA tool should have **independent** workspace in separated directories