58 Commits

Author	SHA1	Message	Date
tangxifan	38218abeda	[Script] Narrow down file modification to XML files	2020-10-09 22:47:32 -06:00
tangxifan	3fb8e425a7	[Script] initial version of setup script	2020-10-09 20:31:13 -06:00
tangxifan	070b0314fd	[Script] Reduce hierarchy level of task configuration files	2020-10-09 20:21:41 -06:00
tangxifan	64043218eb	[Script] Add openfpga task template	2020-10-09 20:11:12 -06:00
tangxifan	72f8323468	[Script] Start developing scripts to initialize the repository	2020-10-09 18:32:59 -06:00
tangxifan	a2b42c2e5f	[Script] Now use variables to redirect the output directory of Verilog/SDC files	2020-10-09 16:00:41 -06:00
tangxifan	b9cbe3c69e	[Flow] Add openfpga task for generate fabric	2020-10-09 15:07:18 -06:00
tangxifan	64bbaf374d	[Flow] Add scripts to run OpenFPGA tasks	2020-10-09 14:49:54 -06:00