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791 Commits 16 Branches 1 Tag 1.8 GiB
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791 Commits

Author SHA1 Message Date
tangxifan b82dbd1a05 [Doc] Update README for python script 2020-11-27 10:29:32 -07:00
tangxifan 864ed26c9a [Arch] Merge latest arch from QuickLogic team on AP3 device using VPR routing architecture 2020-11-27 10:11:40 -07:00
Laboratory for Nano Integrated Systems (LNIS) 5bb0db4e91
Merge pull request #37 from LNIS-Projects/xt_dev 
Python Script to Convert pre-PnR Verilog Testbench to post-PnR Verilog Testbench
 2020-11-26 20:53:21 -07:00
tangxifan feafc46465 [Script] Add python script to convert pre-PnR testbench to post-PnR testbench 2020-11-26 20:47:29 -07:00
tangxifan 2d30c10403 [Script] Now batch task run will error out in the first failed task 2020-11-26 18:30:01 -07:00
tangxifan c237500588 [Script] Remove signal initialization from testbench generator 2020-11-26 18:23:26 -07:00
Laboratory for Nano Integrated Systems (LNIS) 82c00eda30
Merge pull request #36 from LNIS-Projects/xt_dev 
Critical Patch on VPR Arch for Shift Register Implementation
 2020-11-25 20:14:43 -07:00
tangxifan ba17de5509 [Doc] Add description about operating modes of Logic Elements 2020-11-25 17:43:35 -07:00
tangxifan a4f6c34466 [Doc] Add images for multi-mode logic element architecture 2020-11-25 17:17:07 -07:00
tangxifan 0fa3604b6c [Arch] Update arch to enable more routability in shift register mode 2020-11-25 17:04:08 -07:00
tangxifan 6aefa8077e [Arch] Critical patch on LE architecture which enables correct shift register connections 2020-11-25 16:40:54 -07:00
tangxifan fb9834e4e6 [Git] Add .v files to Large file system tracking 2020-11-25 16:04:46 -07:00
tangxifan a92b9ce482 [Arch] Test Quicklogic test architecture 2020-11-25 15:58:50 -07:00
tangxifan 98917a51bc [Testbench] Update post pnr testbench with signal initialization 2020-11-23 16:24:50 -07:00
tangxifan 73de63d41c [Script] update SDF generation script 2020-11-23 16:24:26 -07:00
tangxifan 973fe1acc8 [Script] Add signal initialization to openfpga-run scripts 2020-11-23 15:13:06 -07:00
Ganesh Gore 8053d7e626 Merge remote-tracking branch 'origin/master' into ganesh_dev 2020-11-22 16:37:36 -07:00
Laboratory for Nano Integrated Systems (LNIS) 36a512123a
Merge pull request #35 from LNIS-Projects/xt_dev 
Add microbenchmark and associated Post-PnR testbenches to test fracturable LUT4
 2020-11-22 16:22:35 -07:00
tangxifan 38d15ff0dc
Merge pull request #34 from LNIS-Projects/ganesh_dev 
Added FPGA12x12 with CocoTB tests
 2020-11-22 16:21:50 -07:00
tangxifan 1c40ab68a1 [Testbench] Add post PnR testbench for and2_or2 benchmark 2020-11-22 13:45:16 -07:00
tangxifan e8abcc64bb [Script] Add and2_or2 benchmark to the testbench generation script for 12x12 HD FPGA 2020-11-22 13:34:53 -07:00
tangxifan 6c4c23ee72 [Benchmark] Add benchmark to test fracturable LUTs 2020-11-22 13:33:09 -07:00
ganeshgore 09c7dba92a
Merge pull request #33 from LNIS-Projects/xt_dev 
Caravel Wrapper Update: Use Wishbone Clock as a Regular Input of FPGA
 2020-11-21 16:08:59 -07:00
Ganesh Gore c54cdcd3ef Added FPGA12x12 with CocoTB tests 2020-11-21 16:07:09 -07:00
tangxifan fa9a3bd9f3 [Doc] Minor bug fix in the I/O mapping to wishbone 2020-11-20 18:26:41 -07:00
tangxifan b2573bf242 [Doc] Update I/O resource documentation to synchronize the changes on wrapper 2020-11-20 18:24:29 -07:00
tangxifan b08b77994c [HDL] Bug fix in the wrapper generator; now Wishbone clock is wired to a gpio of FPGA 2020-11-20 18:13:37 -07:00
Laboratory for Nano Integrated Systems (LNIS) 017fb684ae
Merge pull request #32 from LNIS-Projects/xt_dev 
Benchmark and Post-PnR Testbench Update
 2020-11-20 18:00:07 -07:00
tangxifan 06c732325b [Testbench] Add post-PnR testbench for benchmark simon_serial 2020-11-20 17:05:42 -07:00
tangxifan 5edb154140 [Testbench] Add post PnR testbench for benchmark bin2bcd 2020-11-20 16:59:38 -07:00
tangxifan b60e0aa2cd [Testbench] Add post-PnR testbench for benchmark routing_test 2020-11-20 16:47:03 -07:00
tangxifan aa79cc3577 [Testbench] Add post-PnR testbench for benchmark counter 2020-11-20 16:34:32 -07:00
tangxifan a5a92d719a [Script] Remove benchmarks which cannot fit from task-run 2020-11-20 15:44:30 -07:00
Laboratory for Nano Integrated Systems (LNIS) 4d0f50470e
Merge pull request #31 from LNIS-Projects/xt_dev 
Testbench improvements
 2020-11-20 15:37:02 -07:00
tangxifan ce188bbe2c [Script] Add benchmarks to openfpga testbench generator task-run 2020-11-20 15:35:57 -07:00
tangxifan 326c297cb1 [Benchmark] Add more opencore benchmarks for testing 2020-11-20 15:31:58 -07:00
tangxifan b07a156432 [Script] Deploy more testing benchmarks to the OpenFPGA testbench generation task 2020-11-20 15:10:29 -07:00
tangxifan bd17e6b2af [Benchmark] Add more basic benchmarks for post-PnR testing 2020-11-20 15:06:44 -07:00
tangxifan 7145f7ccd4 [Doc] Add documentation about the testbenches 2020-11-20 13:59:15 -07:00
tangxifan 3756c25572 [Testbench] Enhance checking codes. Now 'X' or 'Z' signal will fail in self-checking 2020-11-20 13:51:26 -07:00
tangxifan 5a2f1e7607 [TESTBENCH] Place the include lines for post-PnR skywater cell netlists in a separated netlist, so that it can be shared among post-PnRed testbenches 2020-11-20 13:33:13 -07:00
tangxifan 40eccfa0ba [Testbench] Update post-PnR testbenches for configuration chain and scan-chain and enhance checking codes 2020-11-20 11:45:51 -07:00
tangxifan ae82946052 [Testbench] Update and2_latch post-pnr testbench 2020-11-20 11:15:01 -07:00
tangxifan e58fc97794 [Testbench] Update post-pnr test for latest PnRed netlist 2020-11-20 10:55:59 -07:00
ganeshgore e69e826cd1
Merge pull request #30 from LNIS-Projects/xt_dev 
Update Caravel wrapper generator to use tri-state buffer for wishbone and logic analyzer outputs
 2020-11-20 10:16:43 -07:00
tangxifan 6fa5e935fa [HDL] Update wrapper generator to use tri-state buffer for outputs 2020-11-19 17:14:50 -07:00
tangxifan dde0656968 [HDL] Patch tech mapped netlists of digital I/O and remove the out-of-date behavoiral codes 2020-11-19 16:31:06 -07:00
tangxifan ca716234f1 Merge branch 'master' of https://github.com/LNIS-Projects/skywater-openfpga into xt_dev 2020-11-19 16:14:39 -07:00
tangxifan 95107f9c7a [Doc] Correct bug in I/O circuit design and use svg instead of png in documentation 2020-11-19 16:13:27 -07:00
tangxifan 8036d4f39d
Merge pull request #29 from LNIS-Projects/ganesh_dev 
Ganesh dev
 2020-11-19 14:44:09 -07:00