riscv
/
SOFA
mirror of https://github.com/lnis-uofu/SOFA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
711 Commits 16 Branches 1 Tag 1.8 GiB
Commit Graph

711 Commits

Author SHA1 Message Date
tangxifan 0180a5146f
Merge pull request #62 from lnis-uofu/xt_dev 
Bug fix on the CI dependency for OpenFPGA-run in Github Actions
 2020-12-09 09:53:45 -07:00
Ganesh Gore d9b945ab6f [Actions] Temporarily disable deployment 
+ Magic DRC check fails on CI machine
+ Not enough RAM
+ Will perform test locally and upload
 2020-12-09 01:04:26 -07:00
Ganesh Gore 77bb6d4eae [SOFA_CHD] Added Verification results 2020-12-09 00:55:27 -07:00
Ganesh Gore 45ff6d2dfe [SOFA_CHD] Added post-pnr netlist, Verified CCFF/SCFF 2020-12-09 00:54:03 -07:00
Ganesh Gore 1a2e6de718 [SOFA_CHD] Removed large testbench file 2020-12-09 00:51:30 -07:00
Ganesh Gore 9284bbf8fa [SOFA_CHD] Added OpenFPGA taks and verilog netlist 2020-12-09 00:49:00 -07:00
Ganesh Gore def270a94b [Actions] Launched checker in correct directory 2020-12-08 21:50:18 -07:00
tangxifan 3c9017b2f8 [CI] Bug fix 2020-12-08 16:41:22 -07:00
tangxifan 80937ca769 [CI] Update dependency to sync with OpenFPGA 2020-12-08 16:36:02 -07:00
tangxifan ed92cba451 [HDL] Add netlist for simulation with Caravel + FPGA 2020-12-08 15:35:38 -07:00
Ganesh Gore 3ecd96596f [Actions] Merged Caravel with Klayout 2020-12-08 13:33:17 -07:00
Laboratory for Nano Integrated Systems (LNIS) 06ea86c0b0
Merge pull request #60 from lnis-uofu/xt_dev 
Scripts to Automate the Synthesis for the decoders in FPGAs with custom cells
 2020-12-08 13:30:40 -07:00
Ganesh Gore 2f2b301395 [Action] Updated repo destination 2020-12-08 11:31:04 -07:00
Ganesh Gore 9efe8a7935 [Actions] Added correct repository 2020-12-08 10:24:54 -07:00
tangxifan 3cc54ccb59 [MSIM] Bug fix 2020-12-08 10:15:39 -07:00
tangxifan 4247819ccb Merge branch 'xt_dev' of https://github.com/LNIS-Projects/skywater-openfpga into xt_dev 2020-12-08 10:13:33 -07:00
tangxifan 55ff90905f [DC] Add scripts to automate the synthesis for local encoders 2020-12-08 10:12:57 -07:00
tangxifan 3d2f792fa5
Merge pull request #59 from lnis-uofu/xt_dev 
Now modelsim verification is multithreaded
 2020-12-07 18:53:42 -07:00
tangxifan 77dfb469b5
Update MSIM/common/run_post_pnr_msim_task.py 
Co-authored-by: Ashton Snelgrove <ashton.snelgrove@utah.edu>
 2020-12-07 17:41:22 -07:00
tangxifan 7f9c8e2e90 [Doc] Add Readme for design compiler workspace 2020-12-07 17:40:08 -07:00
tangxifan 2f741ecc15 [MSIM] Now modelsim verification is multithreaded 2020-12-07 15:25:48 -07:00
Ganesh Gore 0e691fe9ca [SOFA-HD] Updated reports and screenshots 2020-12-07 11:55:59 -07:00
Ganesh Gore 40f1e1fae1 Merge remote-tracking branch 'origin/master' into ganesh_dev 2020-12-07 10:14:56 -07:00
Laboratory for Nano Integrated Systems (LNIS) 67e0c94c66
Merge pull request #58 from lnis-uofu/xt_dev 
Scripts for Verifications on Custom Cell -based FPGA (SOFA CHD)
 2020-12-07 09:45:43 -07:00
tangxifan fd074254e9
Merge pull request #57 from lnis-uofu/ganesh_dev 
Added Caravel merge and precheck in action + Updated SOFA-HD and QLSOFA-HD gds
 2020-12-07 09:07:30 -07:00
Ganesh Gore 7967d1da1f [Bugfix] Solved merge conflict 2020-12-06 23:13:59 -07:00
Ganesh Gore 5474ff53c5 [Fixup] Merge conflict with master 2020-12-06 21:41:06 -07:00
Ganesh Gore b90ee124a3 Resolves merge conflict with master 2020-12-06 21:35:34 -07:00
Ganesh Gore b0098ed4b9 Merge remote-tracking branch 'origin/master' into ganesh_dev 2020-12-06 21:29:06 -07:00
Ganesh Gore 5679ee0cb4 [QLSOFA-HD] Fixed reset signal short/GDS precision to 1000 2020-12-06 20:47:52 -07:00
Ganesh Gore 12ffaed8fa [QLSOFA-HD] Added screenshots for top level PnR 2020-12-06 20:45:31 -07:00
tangxifan 7f53e0ef18 [HDL] Add HDL for custom cells 2020-12-06 14:15:03 -07:00
tangxifan aa90424ada [HDL] Add primitive include lines for digital I/O built with HD cells 2020-12-06 11:35:35 -07:00
tangxifan 21a4928002 [HDL] Bug fix in custom cell code generator 2020-12-06 11:28:37 -07:00
tangxifan da08e505b5 [MSIM] Support pre-pnr simulation in script-run verification 2020-12-06 11:13:50 -07:00
Ganesh Gore 328594d8c5 [Action] Clean up action scripts 2020-12-06 01:53:21 -07:00
Ganesh Gore 9322afadad [Action] Added 30 min timeout ticker 2020-12-06 01:42:07 -07:00
Ganesh Gore ea7e2b248b [Action] Testing Docker action 2020-12-06 01:41:58 -07:00
Ganesh Gore 10cab93799 [Action] Integrated MPW prechecker 2020-12-06 01:41:58 -07:00
Ganesh Gore 40c131983a [FPGA1212_v1] Changed gds precision to 1000 2020-12-06 01:41:58 -07:00
Ganesh Gore 6af001df11 Added SynRepoConfig is paths 2020-12-06 01:41:58 -07:00
Ganesh Gore 2bada6124f [Action] Changed Docker workdir 2020-12-06 01:41:46 -07:00
Ganesh Gore cfa2bb96c4 [Action] Removed nojekyll file addition 2020-12-06 01:41:46 -07:00
Ganesh Gore 51cd5d6630 [Action] Added Docker itegration 2020-12-06 01:41:36 -07:00
Ganesh Gore 60060762e5 [Action] Replaced destination repo url 2020-12-06 01:41:00 -07:00
Ganesh Gore 2ecc166e95 [Action] Added destination repo push action 2020-12-06 01:40:38 -07:00
Ganesh Gore 8105a46f07 [Actions] Alternate option to modify file 2020-12-06 01:40:21 -07:00
Ganesh Gore d63dfa00b7 [Actions] filename bugfix 2020-12-06 01:40:21 -07:00
Ganesh Gore 027f0f76a2 [bugfix] Indentation bug in actions yaml 2020-12-06 01:40:21 -07:00
Ganesh Gore 41f2844698 [Action] And modify file and push action 2020-12-06 01:40:21 -07:00