17 Commits

Author	SHA1	Message	Date
Ganesh Gore	7309d3822c	[DRCFix] Fixed filler cell boundary	2021-02-10 22:43:08 -07:00
ganeshgore	5519215882	Merge pull request #95 from lnis-uofu/FPGA1212_QLSOFA_arch_typo ... Fix parsing error in FPGA1212_QLSOFA arch file.	2021-02-09 08:29:46 -07:00
Ganesh Gore	3d9748aa17	[DRCfix] QLSOFA swapped fill cell with decap	2021-02-08 22:34:09 -07:00
WRansohoff	b4e3440972	Fix parsing error in FPGA1212_QLSOFA arch file. ... I was pointed to this task as a starting point for generating an FPGA on the skywater PDK, and I think this small change is necessary to get the task to run with: `python3 openfpga_flow/scripts/run_fpga_task.py FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/`	2021-02-05 11:36:29 -06:00
Lalit Sharma	51f11ee630	Replacing deprecated tile_port syntax	2021-01-12 21:33:53 -08:00
Ganesh Gore	e1a25d61dc	[QLSOFA] Bugfix to fix floating cin net	2020-12-22 00:23:37 -07:00
Ganesh Gore	6ef27d5399	[Cleanup] Removed old task and verilog directories	2020-12-20 10:50:13 -07:00
Ganesh Gore	c36e8d797a	Updated all the results	2020-12-20 03:44:00 -07:00
Ganesh Gore	55acf06335	Updated design with new GDS nad updated verilog netlist	2020-12-20 03:31:26 -07:00
Ganesh Gore	da4ae780a9	[Cleanup] Converted .spef to .spef.gz	2020-12-20 02:10:51 -07:00
tangxifan	f258cefd9a	[QLSOFA-HD] Patch on lvs netlist	2020-12-18 10:55:17 -07:00
Ganesh Gore	7150cc694b	[QLSOFA_HD] Minor updates + Added labels for LVS Fix	2020-12-15 09:17:54 -07:00
Ganesh Gore	e15f319103	[QLSOFA_HD] Updated QLSOFA_HD module files	2020-12-14 13:38:27 -07:00
Ganesh Gore	809b070ce2	[QLSOFA_HD] Updated QLSOFA_HD Verification results	2020-12-14 13:38:08 -07:00
Ganesh Gore	ffa44ff099	[QLSOFA_HD] Updated QLSOFA_HD postPnr Netlist + Caravel DRC clean	2020-12-14 13:37:41 -07:00
Ganesh Gore	4c9a3de34a	[QLSOFA_HD] Updated QLSOFA_HD netlist and task	2020-12-14 13:36:52 -07:00
Ganesh Gore	fa87753d62	[Cleanup] Renamed projects to SOFA-HD and QLSOFA-HD	2020-12-14 00:45:11 -07:00