tangxifan
|
3479502ab7
|
[Script] Update task template for testbench generation
|
2020-10-10 11:32:52 -06:00 |
tangxifan
|
abe56ce2c2
|
[Script] Rename openfpga task directory to avoid name conflicts in OpenFPGA task directory
|
2020-10-10 11:06:28 -06:00 |
tangxifan
|
0557ee2928
|
Merge pull request #1 from LNIS-Projects/xt_dev
Documentation addition
|
2020-10-09 22:48:50 -06:00 |
tangxifan
|
38218abeda
|
[Script] Narrow down file modification to XML files
|
2020-10-09 22:47:32 -06:00 |
tangxifan
|
d963fcab2b
|
[Documentation] Format README
|
2020-10-09 22:41:04 -06:00 |
tangxifan
|
1b0fbed707
|
[Documentation] Format README
|
2020-10-09 22:37:39 -06:00 |
tangxifan
|
cee0fa601e
|
[Documentation] Add README for subdirectories
|
2020-10-09 22:36:43 -06:00 |
tangxifan
|
8e9a5e1c71
|
[Documentation] Update README frontpage
|
2020-10-09 22:17:00 -06:00 |
tangxifan
|
3fb8e425a7
|
[Script] initial version of setup script
|
2020-10-09 20:31:13 -06:00 |
tangxifan
|
8b5a17457c
|
[Architecture] bug fix in openfpga arch
|
2020-10-09 20:30:51 -06:00 |
tangxifan
|
070b0314fd
|
[Script] Reduce hierarchy level of task configuration files
|
2020-10-09 20:21:41 -06:00 |
tangxifan
|
64043218eb
|
[Script] Add openfpga task template
|
2020-10-09 20:11:12 -06:00 |
tangxifan
|
72f8323468
|
[Script] Start developing scripts to initialize the repository
|
2020-10-09 18:32:59 -06:00 |
tangxifan
|
0053c57954
|
[Arch] Update architecture file
|
2020-10-09 18:32:31 -06:00 |
tangxifan
|
069c36cbfc
|
[Architecture] Create template architecture for openfpga
|
2020-10-09 17:28:14 -06:00 |
tangxifan
|
a2b42c2e5f
|
[Script] Now use variables to redirect the output directory of Verilog/SDC files
|
2020-10-09 16:00:41 -06:00 |
tangxifan
|
b9cbe3c69e
|
[Flow] Add openfpga task for generate fabric
|
2020-10-09 15:07:18 -06:00 |
tangxifan
|
241aae76e4
|
[Architecture] Rename architecture file
|
2020-10-09 15:04:21 -06:00 |
tangxifan
|
64bbaf374d
|
[Flow] Add scripts to run OpenFPGA tasks
|
2020-10-09 14:49:54 -06:00 |
tangxifan
|
c5d6bcd15f
|
[Architecture] Add VPR and OpenFPGA architecture description which is binded to skywater 130nm sclib
|
2020-10-09 14:33:42 -06:00 |
Laboratory for Nano Integrated Systems (LNIS)
|
e999a847b4
|
Initial commit
|
2020-10-09 14:16:36 -06:00 |