From fdb37e05592dd75a921247b60a43c54c6d0e495b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 18:09:17 -0600 Subject: [PATCH] [Script] formatting --- SNPS_PT/SCRIPT/report_timing_cb.tcl | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/SNPS_PT/SCRIPT/report_timing_cb.tcl b/SNPS_PT/SCRIPT/report_timing_cb.tcl index c507922..fd5fb73 100644 --- a/SNPS_PT/SCRIPT/report_timing_cb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_cb.tcl @@ -6,16 +6,21 @@ ################################## # Define environment variables set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; + #set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; #set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; + #set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; #set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; + #set DEVICE_NAME "SOFA_HD" set DEVICE_NAME "QLSOFA_HD" #set DEVICE_NAME "SOFA_CHD" + set TIMING_REPORT_HOME "../TIMING_REPORTS/"; + # Enable preprocessing in Verilog parser set_app_var svr_enable_vpp true # Enable reporting ALL the timing paths even those are NOT constrained