Merge pull request #57 from lnis-uofu/ganesh_dev

Added Caravel merge and precheck in action + Updated SOFA-HD and QLSOFA-HD gds

.github/deploy_sofa.yaml

@@ -0,0 +1,80 @@
+name: Caravel-SOFA_HD Deployment
+
+# = = = Env Variable = = = = =
+# secrets.TEST_REPO_KEY
+# secrets.SOFA_HD_KEY
+# secrets.SOFA_CHD_KEY
+# secrets.QLSOFA_HD_KEY
+# secrets.QLAP3_KEY
+# yq r -X deploy_sofa.yaml > ./workflows/deploy_sofa_hd.yaml
+
+env:
+  SCAN_DIRECTORY: &SCAN_DIRECTORY
+    'FPGA1212_FLAT_HD_SKY_PNR/**'
+  PROJ_SUFFIX: &PROJ_SUFFIX
+    SOFA_HD
+  DEST_DIR: &DEST_DIR
+    Caravel-SOFA_HD
+  DEST_REPO: &DEST_REPO
+    lnis-uofu/actions_test_repo
+  REPO_KEY: &REPO_KEY
+    ${{ secrets.TEST_REPO_KEY }}
+
+on:
+  push:
+    paths:
+    - '.github/**'
+    - 'SynRepoConfig/**'
+    - '$SCAN_DIRECTORY'
+  pull_request:
+    types: closed
+    branches:
+      - master
+jobs:
+  linux:
+    name: Updating release repository
+    runs-on: ubuntu-latest
+    steps:
+    - name: Checkout SOFA-Chips
+      uses: actions/checkout@v2
+      with:
+        path: SOFA-Chips
+
+    - name: Checkout caravel repo
+      uses: actions/checkout@master
+      with:
+        repository: *DEST_REPO
+        path: *DEST_DIR
+
+    - name: Checkout open_mpw_precheck repo
+      uses: actions/checkout@master
+      with:
+        repository: efabless/open_mpw_precheck
+        path: open_mpw_precheck
+
+    - name: Perform checks with open_mpw_precheck
+      uses: ganeshgore/docker-run-action@49cd3a1
+      with:
+        image: goreganesh/open_mpw_prechecker
+        options: >
+          -v ${{github.workspace}}/open_mpw_precheck:/usr/local/bin
+          -v ${{github.workspace}}:/usr/local/workspace
+          -e DEST_DIR=$DEST_DIR
+          -e SCAN_DIRECTORY=$SCAN_DIRECTORY
+          --workdir /usr/local/workspace
+        run: cd /usr/local/workspace && pwd && ls && bash ./SOFA-Chips/.github/workflows/perform_precheck.sh
+
+    - name: Deploy files
+      run: bash ./SOFA-Chips/.github/workflows/sync_repo.sh
+
+    - name: Deploy Changes
+      uses: peaceiris/actions-gh-pages@v3
+      with:
+        user_name: "lnis.uofu"
+        user_email: "lnis.uofu@gmail.com"
+        deploy_key: *REPO_KEY
+        external_repository: *DEST_REPO
+        publish_dir: *DEST_DIR
+        publish_branch: master
+        disable_nojekyll: true
+        commit_message: '[Deployment] ${{ github.event.head_commit.message }}'

.github/workflows/build.yml

@@ -6,6 +6,8 @@ name: linux_build
 # - scheduled weekly
 on:
   push:
+    branches-ignore:
+    - ganesh_dev
   pull_request:
   schedule:
     - cron: '0 0 * * 0 ' # weekly

.github/workflows/deploy_sofa_hd.yaml

@@ -0,0 +1,64 @@
+name: Caravel-SOFA_HD Deployment
+# = = = Env Variable = = = = =
+# secrets.TEST_REPO_KEY
+# secrets.SOFA_HD_KEY
+# secrets.SOFA_CHD_KEY
+# secrets.QLSOFA_HD_KEY
+# secrets.QLAP3_KEY
+# yq r -X deploy_sofa.yaml > ./workflows/deploy_sofa_hd.yaml
+env:
+  SCAN_DIRECTORY: 'FPGA1212_FLAT_HD_SKY_PNR/**'
+  PROJ_SUFFIX: SOFA_HD
+  DEST_DIR: Caravel-SOFA_HD
+  DEST_REPO: lnis-uofu/actions_test_repo
+  REPO_KEY: ${{ secrets.TEST_REPO_KEY }}
+on:
+  push:
+    paths:
+      - '.github/**'
+      - 'SynRepoConfig/**'
+      - '$SCAN_DIRECTORY'
+  pull_request:
+    types: closed
+    branches:
+      - master
+jobs:
+  linux:
+    name: Updating release repository
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout SOFA-Chips
+        uses: actions/checkout@v2
+        with:
+          path: SOFA-Chips
+      - name: Checkout caravel repo
+        uses: actions/checkout@master
+        with:
+          repository: lnis-uofu/actions_test_repo
+          path: Caravel-SOFA_HD
+      - name: Checkout open_mpw_precheck repo
+        uses: actions/checkout@master
+        with:
+          repository: efabless/open_mpw_precheck
+          path: open_mpw_precheck
+      - name: Perform checks with open_mpw_precheck
+        uses: ganeshgore/docker-run-action@49cd3a1
+        with:
+          image: goreganesh/open_mpw_prechecker
+          options: >
+            -v ${{github.workspace}}/open_mpw_precheck:/usr/local/bin -v ${{github.workspace}}:/usr/local/workspace -e DEST_DIR=$DEST_DIR -e SCAN_DIRECTORY=$SCAN_DIRECTORY --workdir /usr/local/workspace
+
+          run: cd /usr/local/workspace && pwd && ls && bash ./SOFA-Chips/.github/workflows/perform_precheck.sh
+      - name: Deploy files
+        run: bash ./SOFA-Chips/.github/workflows/sync_repo.sh
+      - name: Deploy Changes
+        uses: peaceiris/actions-gh-pages@v3
+        with:
+          user_name: "lnis.uofu"
+          user_email: "lnis.uofu@gmail.com"
+          deploy_key: ${{ secrets.TEST_REPO_KEY }}
+          external_repository: lnis-uofu/actions_test_repo
+          publish_dir: Caravel-SOFA_HD
+          publish_branch: master
+          disable_nojekyll: true
+          commit_message: '[Deployment] ${{ github.event.head_commit.message }}'

.github/workflows/perform_precheck.sh

@@ -0,0 +1,51 @@
+#!/bin/bash
+
+# Working directory in github workspace
+# Original repo is places ../SOFA-Chips
+# for conditional file copy use PROJ_SUFFIX (example SOFA_HD)
+
+cd ./${DEST_DIR}
+echo "[Info] Running in directory ${PWD}"
+
+cp ../SOFA-Chips/${SCAN_DIRECTORY}/fpga_top_icv_in_design.gds.gz ./gds/
+make uncompress
+echo "[Info] All files are uncompressed"
+
+# = = = = = = = = = = = =  Modify Merge Scripts = = = = = = = = = = = = = = = =
+AddLine="use fpga_top fpga_top_uut\n"\
+"transform 1 0 0 0 1 0\n"\
+"box 0 0 2500 3000"
+sed -i "s/<< properties >>/${AddLine}\n<< properties >>/" ./mag/user_project_wrapper.mag
+# Running magic to merge fpga_top
+MAGTYPE=mag \
+magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/current/sky130A.magicrc \
+-noconsole -dnull \
+../SOFA-Chips/SCRIPT/merge_fpga_top.tcl </dev/null | tee magic_drc.log
+echo "[Info] merge fpga-top"
+
+# = = = = = = = = = = = = = Build Caravel = = = = = = = = = = = = = = = = = = =
+for i in {1..30}; do sleep 1m; echo "Still shipping"; done & # 30 min timeout for merge GDS
+make ship
+kill %1
+echo "[Info] Finished shiping chip"
+rm -f gds/caravel.old.gds
+
+# = = = = = = = = = = = = = Perform Open MPW Checks = = = = = = = = = = = = = =
+python3 /usr/local/bin/open_mpw_prechecker.py \
+    --target_path /usr/local/workspace/${DEST_DIR} \
+    --pdk_root $PDK_ROOT
+echo "[Info] Finished MPW Prechecker"
+
+# = = = = = = = Convert DRC Errors to RDB = = = = = = = = = = = = = = = = = = =
+if test -f "./checks/caravel.magic.drc"; then
+    python3 ../SOFA-Chips/SCRIPT/magic_drc_to_rdb.py \
+        -magic_drc_in ./checks/caravel.magic.drc
+        -rdb_out ./checks/caravel.magic.rdb
+fi
+echo "[Info] Converted errors in RDB format"
+
+# = = = = = = = Clean up repo  = = = = = = = = = = = = = = = = = = =
+rm -rf user_project_wrapper.mag
+rm -rf gds/caravel.mag
+rm -rf magic_drc.log
+git checkout HEAD -- ./mag/user_project_wrapper.mag

.github/workflows/sync_repo.sh

@@ -0,0 +1,19 @@
+#!/bin/bash
+# This script runs after the prechecks and before the deployment
+# In the host enviroment (All the GITHUB variables are available)
+
+# Working directory in github workspace
+# Original repo is places SOFA-Chips
+# for conditional file copy use PROJ_SUFFIX (example SOFA_HD)
+
+tail -n +2 ./SOFA-Chips/SynRepoConfig/sync_files.csv | while  IFS=, read -r srcLoc dstLoc; do
+    Copying "./SOFA-Chips/$srcLoc --> ${DEST_DIR}/$dstLoc"
+    rsync -avp ./SOFA-Chips/$srcLoc ${DEST_DIR}/$dstLoc
+done
+
+cd ${DEST_DIR}
+
+[ -s source_commit_hash.txt ] || echo "----------" > source_commit_hash.txt
+sed -i -e "s/^/\n/" source_commit_hash.txt
+sed -i -e "s/^/${GITHUB_SHA}\n/" source_commit_hash.txt
+sed -i -e "s/^/$(date)\n/" source_commit_hash.txt

SCRIPT/magic_drc_to_rdb.py

@@ -0,0 +1,62 @@
+
+import os
+import sys
+import re
+import shutil
+import argparse
+import math
+
+
+def formatter(prog): return argparse.HelpFormatter(prog, max_help_position=60)
+
+
+parser = argparse.ArgumentParser(formatter_class=formatter)
+
+# Mandatory arguments
+parser.add_argument('--magic_drc_in', type=str, default="./checks/caravel.magic.drc")
+parser.add_argument('--rdb_out', type=str, default="./checks/caravel.magic.rdb")
+args = parser.parse_args()
+
+data, drc = True, False
+def main():
+    try:
+        fp = open(args.magic_drc_in)
+        lineType = data
+        drcRule = ""
+        with open(args.rdb_out,"w") as fpw:
+            for line in fp.readlines():
+                if ("[INFO]" in line) or (len(line.strip())==0):
+                    continue
+                elif ("caravel" in line):
+                    fpw.write("caravel 100\n")
+                elif "------" in line:
+                    lineType = not lineType
+                elif (lineType==drc):
+                    drcRule = line.strip().split("(")
+                    drcRule = [drcRule,"UnknownRule"] if len(drcRule) <2 else drcRule
+                    fpw.write(f"r_0_{drcRule[1][:-1]}\n")
+                    fpw.write(f"500 500 2 Nov 29 03:26:39 2020\n")
+                    fpw.write(f"Rule File Pathname: {args.magic_drc_in}\n")
+                    fpw.write(f"{drcRule[1][:-1]}: {drcRule[0]}\n")
+                    drcNumber = 1
+                elif (lineType==data):
+                    cord = [int(float(i))*100 for i in line.strip().split(" ")]
+                    fpw.write(f"p {drcNumber} 4\n")
+                    fpw.write(f"{cord[0]} {cord[1]}\n")
+                    fpw.write(f"{cord[2]} {cord[1]}\n")
+                    fpw.write(f"{cord[2]} {cord[3]}\n")
+                    fpw.write(f"{cord[0]} {cord[3]}\n")
+                    drcNumber+=1
+        print(f"Generated RDB at {args.rdb_out}")
+
+
+    except IOError:
+        print("Magic DRC Error file not found {args.magic_drc_in}")
+    except:
+        print("Failed to generate RDB file")
+    finally:
+        fp.close()
+
+
+if __name__ == "__main__":
+    main()

SCRIPT/merge_fpga_top.tcl

@@ -0,0 +1,14 @@
+drc off
+gds readonly true
+gds rescale false
+gds merge yes
+
+gds read ./gds/fpga_top_icv_in_design.gds
+load ./mag/user_project_wrapper.mag
+
+save user_project_wrapper
+
+select top cell
+gds write ./gds/user_project_wrapper.gds
+
+exit

SynRepoConfig/sync_files.csv

@@ -0,0 +1,2 @@
+SrcLoc, DestLoc
+FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/,OpenFPGA_task