From fc3eadaf29e48f0b030b39bf6baa7dd8a2264259 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 29 Nov 2020 22:58:48 -0700 Subject: [PATCH] [Testbench] Add SCFF test for wrapper --- .../postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v | 3 +++ .../scff_test_post_pnr_wrapper_include_netlists.v | 3 +++ 2 files changed, 6 insertions(+) create mode 100644 TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v create mode 100644 TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v new file mode 100644 index 0000000..fa2dc67 --- /dev/null +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:aa307fe506d4107e78867547f28e9533691c57b6ccea22f24afb389b7d61ce5a +size 29307 diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v new file mode 100644 index 0000000..8f290f1 --- /dev/null +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:33fd521a78b634170da832cd9e481ffd8005682dee862c51c359b5edc6978e7a +size 1391