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update header for description

This commit is contained in:
Kevin Liao 2021-01-26 10:10:35 -08:00
parent f0050b851d
commit f7feca6686
1 changed files with 4 additions and 15 deletions
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19
HDL/common/ql_ccff.v
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@ -1,21 +1,10 @@
`timescale 1ns/1ps `timescale 1ns/1ps
//----------------------------------------------------- //-----------------------------------------------------
// Function : An embedded I/O with // Function : QuickLogic physical CCFF
// - An I/O isolation signal to set // - intorduce CFGE to gate CCFF output for
// the I/O in input mode. This is to avoid // un-wanted toggling during configuration
// any unexpected output signals to damage // - intorduce test data in, SI, for DFM
// circuits outside the FPGA due to configurable
// memories are not properly initialized
// This feature may not be needed if the configurable
// memory cell has a built-in set/reset functionality
// - Internal protection circuitry to ensure
// clean signals at all the SOC I/O ports
// This is to avoid
// - output any random signal
// when the I/O is in input mode, also avoid
// - driven by any random signal
// when the I/O is output mode
// //
// Note: This cell is built with Standard Cells from HD library // Note: This cell is built with Standard Cells from HD library
// It is already technology mapped and can be directly used // It is already technology mapped and can be directly used