From f5d18d33ea9d328daca155ba38c1dad9084fb192 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 18 Nov 2020 16:23:37 -0700 Subject: [PATCH] [Testbench] Add scan-chain testbench for post-pnr verification --- TESTBENCH/common/post_pnr_scff_test.v | 179 ++++++++++++++++++ .../scff_test_post_pnr_include_netlists.v | 69 +++++++ 2 files changed, 248 insertions(+) create mode 100644 TESTBENCH/common/post_pnr_scff_test.v create mode 100644 TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v diff --git a/TESTBENCH/common/post_pnr_scff_test.v b/TESTBENCH/common/post_pnr_scff_test.v new file mode 100644 index 0000000..4b6c15b --- /dev/null +++ b/TESTBENCH/common/post_pnr_scff_test.v @@ -0,0 +1,179 @@ +//------------------------------------------- +// Verilog Testbench for Verifying +// Scan Chain of a FPGA +// Description: This test is applicable to FPGAs which have a built-in scan +// chain. It will feed a pulse to the head of the scan chain and +// check if the pulse is outputted by the tail of the can chain +// in a given time period +// +// Note: This test bench is tuned for the pre PnR netlists +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +//`define FPGA_IO_SIZE 144 +// +// Design parameter for FPGA scan-chain sizes +//`define FPGA_SCANCHAIN_SIZE 2304 + +module post_pnr_scff_test; +// ----- Local wires for global ports of FPGA fabric ----- +wire [0:0] prog_clk; +wire [0:0] Test_en; +wire [0:0] clk; + +// ----- Local wires for I/Os of FPGA fabric ----- + +wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; +wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; +wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + +reg [0:0] prog_clock_reg; +wire [0:0] prog_clock; +wire [0:0] op_clock; +reg [0:0] op_clock_reg; +reg [0:0] prog_reset; +reg [0:0] prog_set; +reg [0:0] greset; +reg [0:0] gset; +// ---- Configuration-chain head ----- +wire [0:0] ccff_head; +// ---- Configuration-chain tail ----- +wire [0:0] ccff_tail; + +// ---- Scan-chain head ----- +reg [0:0] sc_head; +// ---- Scan-chain tail ----- +wire [0:0] sc_tail; + +wire [0:0] IO_ISOL_N; + +// ----- Counters for error checking ----- +integer num_clock_cycles = 0; +integer num_errors = 0; + +// Indicate when configuration should be finished +reg scan_done = 0; + +initial + begin + scan_done = 1'b0; + end + +// ----- Begin raw programming clock signal generation ----- +initial + begin + prog_clock_reg[0] = 1'b0; + end +// ----- End raw programming clock signal generation ----- + +// ----- Begin raw operating clock signal generation ----- +initial + begin + op_clock_reg[0] = 1'b0; + end +always + begin + #5 op_clock_reg[0] = ~op_clock_reg[0]; + end + +// ----- End raw operating clock signal generation ----- +// ----- Actual operating clock is triggered only when scan_done is enabled ----- + assign prog_clock[0] = prog_clock_reg[0] & ~greset; + assign op_clock[0] = op_clock_reg[0] & ~greset; + +// ----- Begin programming reset signal generation ----- +initial + begin + prog_reset[0] = 1'b0; + end + +// ----- End programming reset signal generation ----- + +// ----- Begin programming set signal generation ----- +initial + begin + prog_set[0] = 1'b0; + end + +// ----- End programming set signal generation ----- + +// ----- Begin operating reset signal generation ----- +// ----- Reset signal is disabled always ----- +initial + begin + greset[0] = 1'b1; + #10 greset[0] = 1'b0; + end + +// ----- End operating reset signal generation ----- +// ----- Begin operating set signal generation: always disabled ----- +initial + begin + gset[0] = 1'b0; + end + +// ----- End operating set signal generation: always disabled ----- + +// ----- Begin connecting global ports of FPGA fabric to stimuli ----- + assign clk[0] = op_clock[0]; + assign prog_clk[0] = prog_clock[0]; + assign Test_en[0] = ~greset; + assign ccff_head[0] = 1'b0; + assign IO_ISOL_N[0] = 1'b0; +// ----- End connecting global ports of FPGA fabric to stimuli ----- +// ----- FPGA top-level module to be capsulated ----- + fpga_core FPGA_DUT ( + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1]), + .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1]), + .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:`FPGA_IO_SIZE - 1]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail[0]), + .sc_head(sc_head[0]), + .sc_tail(sc_tail[0]) + //.IO_ISOL_N(IO_ISOL_N) + ); + +// ----- Force constant '0' to FPGA I/O as this testbench only check +// programming phase ----- + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}}; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}}; + +// Generate a pulse after operating reset is disabled (in the 2nd clock +// cycle). Then the head of scan chain should be always zero + always @(negedge op_clock[0]) begin + sc_head = 1'b1; + if (0 != num_clock_cycles) begin + sc_head = 1'b0; + end + end + +// ----- Count the number of programming cycles ------- + always @(posedge op_clock[0]) begin + num_clock_cycles = num_clock_cycles + 1; + // Indicate when scan chain loading is suppose to end + if (`FPGA_SCANCHAIN_SIZE + 1 == num_clock_cycles) begin + scan_done = 1'b1; + end + + // Check the tail of scan-chain when configuration is done + if (1'b1 == scan_done) begin + if (sc_tail != 1'b1) begin + $display("Error: sc_tail = %b", sc_tail); + num_errors = num_errors + 1; + end + + $display("Simulation finish with %d errors", num_errors); + + // End simulation + $finish; + end + end + +endmodule diff --git a/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v new file mode 100644 index 0000000..6734773 --- /dev/null +++ b/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -0,0 +1,69 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 108 + +// Design parameter for FPGA bitstream sizes +`define FPGA_SCANCHAIN_SIZE 2304 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" + +// ------ Include Skywater cell netlists ----- +// Cells already used pre-PnR +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v" + +// Cells added due to their use in PnR +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v" + +// ------ Include fabric top-level netlists ----- +//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_scff_test.v"