mirror of https://github.com/lnis-uofu/SOFA.git
Merge pull request #56 from lnis-uofu/xt_dev
Python script to adapt OpenFPGA netlist to use custom MUX cells
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Laboratory for Nano Integrated Systems (LNIS)
GitHub
commit
f572be8fc2
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@ -12,6 +12,9 @@ set -e
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# - Run FPGA tasks to validate netlist generations
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python3 SCRIPT/repo_setup.py --openfpga_root_path ./OpenFPGA
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# Post processing netlist to use custom cells
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python3 HDL/common/custom_cell_mux_primitive_generator.py --template_netlist HDL/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/SRC/sub_module/mux_primitives.v --output_verilog HDL/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/SRC/sub_module/mux_primitives_hd.v
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##############################################
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# Generate wrapper HDL codes to bridge Caravel I/Os and FPGA I/Os
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python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/caravel_fpga_wrapper_hd_template.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --output_verilog HDL/common/caravel_fpga_wrapper_hd_v1.0.v
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@ -30,3 +33,4 @@ python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_test
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# Generate wrapper testbenches from template tesbenches for scan chain tests
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python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/scff_test_post_pnr_v1.0.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --wrapper_testbench TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v
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python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/scff_test_post_pnr_v1.1.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.1.json --wrapper_testbench TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v
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@ -43,6 +43,18 @@
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_1" prefix="sky130_fd_sc_hd__buf_1" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v">
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<design_technology type="cmos" topology="buffer" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
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<device_technology device_model_name="logic"/>
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@ -160,7 +172,7 @@
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<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
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<input_buffer exist="false"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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@ -169,7 +181,7 @@
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<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
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<input_buffer exist="false"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_4"/>
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<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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@ -0,0 +1,179 @@
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#####################################################################
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# Python script generate Verilog codes for the primitive modules
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# that is used to build routing multiplexers
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# The Verilog codes will exploit the custom cells built for MUX primitives
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# including:
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# - 2-input MUX
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# - 3-input MUX
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# - Skywater MUX2 standard cell
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#####################################################################
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import os
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from os.path import dirname, abspath, isfile
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import shutil
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import re
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import argparse
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import logging
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import json
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#####################################################################
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# Initialize logger
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#####################################################################
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logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.DEBUG)
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#####################################################################
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# Parse the options
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# - OpenFPGA root path is a manadatory option
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#####################################################################
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parser = argparse.ArgumentParser(
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description='Generator for custom cells of routing multiplexer primitives')
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parser.add_argument('--template_netlist', required=True,
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help='Specify template verilog netlist')
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parser.add_argument('--output_verilog', required=True,
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help='Specify output verilog file path')
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args = parser.parse_args()
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#####################################################################
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# Check options:
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# - Input file must be valid
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# Otherwise, error out
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# - Remove any output file if already exist
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# TODO: give a warning when remove files
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#####################################################################
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if not isfile(args.template_netlist):
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logging.error("Invalid template netlist: " + args.template_netlist + "\nFile does not exist!\n")
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exit(1)
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if isfile(args.output_verilog):
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logging.warn("Remove existing output netlist: " + args.output_verilog + "!\n")
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os.remove(args.output_verilog)
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#####################################################################
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# Open the template Verilog netlist and start modification
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#####################################################################
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logging.info("Converting template netlist:"+ args.template_netlist)
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logging.info(" To custom cell netlist:"+ args.output_verilog)
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# Create output file handler
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custom_nlist = open(args.output_verilog, "w")
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#######################################################################
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# A function to generate Verilog codes for a MUX3 custom cell
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# Given an input index
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def generate_verilog_codes_custom_cell_mux3(first_input_index, instance_index):
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lines = []
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lines.append("\tscs8hd_muxinv3_1 scs8hd_muxinv3_1_" + str(instance_index) + "(")
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lines.append("\t .Q1(in[" + str(first_input_index) + "]),")
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lines.append("\t .Q2(in[" + str(first_input_index + 1) + "]),")
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lines.append("\t .Q3(in[" + str(first_input_index + 2) + "]),")
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lines.append("\t .S0(mem[" + str(first_input_index) + "]),")
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lines.append("\t .S0B(mem_inv[" + str(first_input_index) + "]),")
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lines.append("\t .S1(mem[" + str(first_input_index + 1) + "]),")
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lines.append("\t .S1B(mem_inv[" + str(first_input_index + 1) + "]),")
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lines.append("\t .S2(mem[" + str(first_input_index + 2) + "]),")
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lines.append("\t .S2B(mem_inv[" + str(first_input_index + 2) + "]),")
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lines.append("\t .Z(out[0])")
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lines.append("\t );")
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return lines
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#######################################################################
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# A function to generate Verilog codes for a MUX3 custom cell
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# Given an input index
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def generate_verilog_codes_custom_cell_mux2(first_input_index, instance_index):
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lines = []
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lines.append("\tscs8hd_muxinv2_1 scs8hd_muxinv2_1_" + str(instance_index) + "(")
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lines.append("\t .Q1(in[" + str(first_input_index) + "]),")
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lines.append("\t .Q2(in[" + str(first_input_index + 1) + "]),")
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lines.append("\t .S0(mem[" + str(first_input_index) + "]),")
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lines.append("\t .S0B(mem_inv[" + str(first_input_index) + "]),")
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lines.append("\t .S1(mem[" + str(first_input_index + 1) + "]),")
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lines.append("\t .S1B(mem_inv[" + str(first_input_index + 1) + "]),")
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lines.append("\t .Z(out[0])")
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lines.append("\t );")
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return lines
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#######################################################################
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# A function to output custom cells of multiplexing structure to a file
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# based on the input size and memory size
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# - If the memory size is 1, the input size should be 2
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# In this case, an standard cell will be outputted
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# - If the memory size is larger than 1, the input size should be the same
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# as memory size. In this case, we will output custom cells
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def write_custom_mux_cells_to_file(custom_nlist, input_size, mem_size):
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lines = []
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if (1 == mem_size):
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assert(2 == input_size)
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# Output a standard cell, currently we support HD cell MUX2
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lines.append("\tsky130_fd_sc_hd_mux2_1 sky130_fd_sc_hd_mux2_1_0(")
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lines.append("\t .A1(in[0]),")
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lines.append("\t .A0(in[1]),")
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lines.append("\t .S(mem[0]),")
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lines.append("\t .X(out[0])")
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lines.append("\t );")
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else:
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assert(1 < mem_size)
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assert(mem_size == input_size)
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# Currently we support MUX2 and MUX3 custom cells
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# - If the input size is an odd number, we will use
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# - 1 MUX3 cell
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# - a few MUX2 cells
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if (1 == input_size % 2):
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assert(3 <= input_size)
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for line in generate_verilog_codes_custom_cell_mux3(0, 0):
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lines.append(line)
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for mux2_inst in range(int((input_size - 3) / 2)):
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for line in generate_verilog_codes_custom_cell_mux2(3 + 2 * mux2_inst, mux2_inst):
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lines.append(line)
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# - If the input size is an even number, we will use
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# - a few MUX2 cells
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else:
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assert (0 == input_size % 2)
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for mux2_inst in range(int(input_size / 2)):
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for line in generate_verilog_codes_custom_cell_mux2(2 * mux2_inst, mux2_inst):
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lines.append(line)
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# Output lines to file
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for line in lines:
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custom_nlist.write(line + "\n")
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# Read line by line from template netlist
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with open(args.template_netlist, "r") as wp:
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template_nlist = wp.readlines()
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# A flag for write the current line or skip
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output_action = "copy"
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input_size = 0
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mem_size = 0
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for line_num, curr_line in enumerate(template_nlist):
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# If the current line satisfy the following conditions
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# It should be modified and outputted to custom netlist
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# Other lines can be directly copied to custom netlist
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line2output = curr_line
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# Once current line starts with a module definition
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# Find the input size and memory size
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if (curr_line.startswith("module ")):
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input_size = int(re.findall("input(\d+)_mem(\d+)\(", curr_line)[0][0])
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mem_size = int(re.findall("input(\d+)_mem(\d+)\(", curr_line)[0][1])
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assert(input_size > 0)
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assert(mem_size > 0)
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# Change status indicating that we are now inside a module
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output_action = "copy"
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# If a line contains the keyword TGATE
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# we will bypass all the lines until reach the endmodule line
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if (curr_line.startswith("\tTGATE TGATE")):
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output_action = "skip"
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# Reaching the end of the current module
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# Now output the custom cell instanciation
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if (curr_line.startswith("endmodule")):
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write_custom_mux_cells_to_file(custom_nlist, input_size, mem_size)
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output_action = "copy"
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if ("skip" != output_action):
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custom_nlist.write(line2output)
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custom_nlist.close()
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logging.info("Done")
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