From f28ff97b8b5c5b290cda66ecfac4a82dc7cb4df6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 20:28:38 -0600 Subject: [PATCH] [Arch] Move timing values to design variable yml so that we can reuse arch XML to model timing in different corners --- ...l_io_skywater130nm_timing_tt_025C_1v80.yml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml diff --git a/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml new file mode 100644 index 0000000..98481e8 --- /dev/null +++ b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml @@ -0,0 +1,26 @@ +L1_SB_MUX_DELAY: 1.61e-9 +L2_SB_MUX_DELAY: 1.61e-9 +L4_SB_MUX_DELAY: 1.61e-9 +CB_MUX_DELAY: 1.38e-9 +L1_WIRE_R: 100 +L1_WIRE_C: 1e-12 +L2_WIRE_R: 100 +L2_WIRE_C: 1e-12 +L4_WIRE_R: 100 +L4_WIRE_C: 1e-12 +INPAD_DELAY: 0.11e-9 +OUTPAD_DELAY: 0.11e-9 +FF_T_SETUP: 0.39e-9 +FF_CLK2Q_DELAY: 0.43e-9 +LUT_OUT0_TO_FF_D_DELAY: 1.14e-9 +LUT_OUT1_TO_FF_D_DELAY: 0.56e-9 +LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 +FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 +LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 +FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 +LUT3_DELAY: 2.31e-9 +LUT3_OUT_TO_FLE_OUT_DELAY: 2.03e-9 +LUT4_DELAY: 2.6e-9 +LUT4_OUT_TO_FLE_OUT_DELAY: 2.03e-9 +REGIN_TO_FF0_DELAY: 1.12e-9 +FF0_TO_FF1_DELAY: 0.56e-9