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[Arch] Bug fix in the architecture using reset

This commit is contained in:
tangxifan 2020-11-27 15:04:19 -07:00
parent 91edfb8e02
commit f27424c803
1 changed files with 3 additions and 2 deletions
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5
ARCH/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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@ -132,7 +132,7 @@
<input name="I7i" num_pins="1" equivalent="none"/> <input name="I7i" num_pins="1" equivalent="none"/>
<input name="reg_in" num_pins="1"/> <input name="reg_in" num_pins="1"/>
<input name="sc_in" num_pins="1"/> <input name="sc_in" num_pins="1"/>
<input name="reset" num_pins="1"/> <input name="reset" num_pins="1" is_non_clock_global="true"/>
<output name="O" num_pins="16" equivalent="none"/> <output name="O" num_pins="16" equivalent="none"/>
<output name="reg_out" num_pins="1"/> <output name="reg_out" num_pins="1"/>
<output name="sc_out" num_pins="1"/> <output name="sc_out" num_pins="1"/>
@ -341,7 +341,7 @@
<input name="I7i" num_pins="1" equivalent="none"/> <input name="I7i" num_pins="1" equivalent="none"/>
<input name="reg_in" num_pins="1"/> <input name="reg_in" num_pins="1"/>
<input name="sc_in" num_pins="1"/> <input name="sc_in" num_pins="1"/>
<input name="reset" num_pins="1"/> <input name="reset" num_pins="1" is_non_clock_global="true"/>
<output name="O" num_pins="16" equivalent="none"/> <output name="O" num_pins="16" equivalent="none"/>
<output name="reg_out" num_pins="1"/> <output name="reg_out" num_pins="1"/>
<output name="sc_out" num_pins="1"/> <output name="sc_out" num_pins="1"/>
@ -649,6 +649,7 @@
<!-- TODO: Timing should be backannotated from post-PnR results --> <!-- TODO: Timing should be backannotated from post-PnR results -->
</direct> </direct>
<complete name="clks" input="clb.clk" output="fle[7:0].clk"> <complete name="clks" input="clb.clk" output="fle[7:0].clk">
</complete>
<complete name="resets" input="clb.reset" output="fle[7:0].reset"> <complete name="resets" input="clb.reset" output="fle[7:0].reset">
</complete> </complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins. <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.