diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v
index 87c2891..c372496 100644
--- a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v
+++ b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v
@@ -4015,15 +4015,15 @@ wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
 supply1 VDD ;
 supply0 VSS ;
 
-assign Test_en_S_in = Test_en_E_in ;
-assign Test_en_W_in = Test_en_E_in ;
-assign Reset_S_in = Reset_E_in ;
-assign Reset_W_in = Reset_E_in ;
+assign Test_en_E_in = Test_en_S_in ;
+assign Test_en_E_in = Test_en_W_in ;
+assign Reset_E_in = Reset_S_in ;
+assign Reset_E_in = Reset_W_in ;
 assign prog_clk_0 = prog_clk[0] ;
-assign prog_clk_2_N_in = prog_clk_2_S_in ;
-assign prog_clk_3_S_in = prog_clk_3_N_in ;
-assign clk_2_N_in = clk_2_S_in ;
-assign clk_3_S_in = clk_3_N_in ;
+assign prog_clk_2_S_in = prog_clk_2_N_in ;
+assign prog_clk_3_N_in = prog_clk_3_S_in ;
+assign clk_2_S_in = clk_2_N_in ;
+assign clk_3_N_in = clk_3_S_in ;
 
 cby_1__1__mux_tree_tapbuf_size12_0 mux_right_ipin_0 (
     .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
@@ -6829,7 +6829,7 @@ wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ;
 supply1 VDD ;
 supply0 VSS ;
 
-assign pReset_E_in = pReset_W_in ;
+assign pReset_W_in = pReset_E_in ;
 assign prog_clk_0 = prog_clk[0] ;
 
 cbx_1__2__mux_tree_tapbuf_size12_0 mux_bottom_ipin_0 (
@@ -8937,14 +8937,14 @@ wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
 supply1 VDD ;
 supply0 VSS ;
 
-assign pReset_E_in = pReset_W_in ;
+assign pReset_W_in = pReset_E_in ;
 assign prog_clk_0 = prog_clk[0] ;
-assign prog_clk_1_W_in = prog_clk_1_E_in ;
-assign prog_clk_2_E_in = prog_clk_2_W_in ;
-assign prog_clk_3_W_in = prog_clk_3_E_in ;
-assign clk_1_W_in = clk_1_E_in ;
-assign clk_2_E_in = clk_2_W_in ;
-assign clk_3_W_in = clk_3_E_in ;
+assign prog_clk_1_E_in = prog_clk_1_W_in ;
+assign prog_clk_2_W_in = prog_clk_2_E_in ;
+assign prog_clk_3_E_in = prog_clk_3_W_in ;
+assign clk_1_E_in = clk_1_W_in ;
+assign clk_2_W_in = clk_2_E_in ;
+assign clk_3_E_in = clk_3_W_in ;
 
 cbx_1__1__mux_tree_tapbuf_size12_0 mux_top_ipin_0 (
     .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
@@ -11473,7 +11473,7 @@ wire [0:0] logical_tile_io_mode_io__7_ccff_tail ;
 supply1 VDD ;
 supply0 VSS ;
 
-assign pReset_E_in = pReset_W_in ;
+assign pReset_W_in = pReset_E_in ;
 assign prog_clk_0 = prog_clk[0] ;
 
 cbx_1__0__mux_tree_tapbuf_size12_0 mux_top_ipin_0 (
@@ -27005,8 +27005,8 @@ wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
 supply1 VDD ;
 supply0 VSS ;
 
-assign pReset_S_in = pReset_E_in ;
-assign pReset_W_in = pReset_E_in ;
+assign pReset_E_in = pReset_S_in ;
+assign pReset_E_in = pReset_W_in ;
 assign prog_clk_0 = prog_clk[0] ;
 
 sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_0 (
@@ -31952,23 +31952,23 @@ assign clk_3_E_out = clk_3_E_in ;
 assign clk_3_W_out = clk_3_E_in ;
 assign clk_3_N_out = clk_3_E_in ;
 assign clk_3_S_out = clk_3_E_in ;
-assign pReset_S_in = pReset_E_in ;
-assign pReset_W_in = pReset_E_in ;
+assign pReset_E_in = pReset_S_in ;
+assign pReset_E_in = pReset_W_in ;
 assign prog_clk_0 = prog_clk[0] ;
-assign prog_clk_1_N_in = prog_clk_1_S_in ;
-assign prog_clk_2_N_in = prog_clk_2_E_in ;
-assign prog_clk_2_S_in = prog_clk_2_E_in ;
-assign prog_clk_2_W_in = prog_clk_2_E_in ;
-assign prog_clk_3_W_in = prog_clk_3_E_in ;
-assign prog_clk_3_S_in = prog_clk_3_E_in ;
-assign prog_clk_3_N_in = prog_clk_3_E_in ;
-assign clk_1_N_in = clk_1_S_in ;
-assign clk_2_N_in = clk_2_E_in ;
-assign clk_2_S_in = clk_2_E_in ;
-assign clk_2_W_in = clk_2_E_in ;
-assign clk_3_W_in = clk_3_E_in ;
-assign clk_3_S_in = clk_3_E_in ;
-assign clk_3_N_in = clk_3_E_in ;
+assign prog_clk_1_S_in = prog_clk_1_N_in ;
+assign prog_clk_2_E_in = prog_clk_2_N_in ;
+assign prog_clk_2_E_in = prog_clk_2_S_in ;
+assign prog_clk_2_E_in = prog_clk_2_W_in ;
+assign prog_clk_3_E_in = prog_clk_3_W_in ;
+assign prog_clk_3_E_in = prog_clk_3_S_in ;
+assign prog_clk_3_E_in = prog_clk_3_N_in ;
+assign clk_1_S_in = clk_1_N_in ;
+assign clk_2_E_in = clk_2_N_in ;
+assign clk_2_E_in = clk_2_S_in ;
+assign clk_2_E_in = clk_2_W_in ;
+assign clk_3_E_in = clk_3_W_in ;
+assign clk_3_E_in = clk_3_S_in ;
+assign clk_3_E_in = clk_3_N_in ;
 
 sb_1__1__mux_tree_tapbuf_size11_0 mux_top_track_0 (
     .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , 
@@ -36254,8 +36254,8 @@ wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ;
 supply1 VDD ;
 supply0 VSS ;
 
-assign pReset_S_in = pReset_E_in ;
-assign pReset_W_in = pReset_E_in ;
+assign pReset_E_in = pReset_S_in ;
+assign pReset_E_in = pReset_W_in ;
 assign prog_clk_0 = prog_clk[0] ;
 
 sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_0 (
@@ -53152,13 +53152,13 @@ wire [0:0] Test_en ;
 supply1 VDD ;
 supply0 VSS ;
 
-assign SC_IN_TOP = SC_IN_BOT ;
-assign Test_en_E_in = Test_en_W_in ;
-assign Reset_E_in = Reset_W_in ;
+assign SC_IN_BOT = SC_IN_TOP ;
+assign Test_en_W_in = Test_en_E_in ;
+assign Reset_W_in = Reset_E_in ;
 assign prog_clk[0] = prog_clk_0 ;
-assign prog_clk_0_N_in = prog_clk_0_S_in ;
+assign prog_clk_0_S_in = prog_clk_0_N_in ;
 assign clk_0 = clk[0] ;
-assign clk_0_N_in = clk_0_S_in ;
+assign clk_0_S_in = clk_0_N_in ;
 
 grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( 
     .pReset ( pReset ) ,