From f028437fefab519e12d24b4bc20c6338d4d96e7c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Dec 2020 16:24:56 -0700 Subject: [PATCH] [Testbench] Update SCFF test to be compatible with simulation with power pins --- .../scff_test_post_pnr_include_netlists.v | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index 24708c9..72bdd92 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -14,15 +14,28 @@ // Design parameter for FPGA bitstream sizes `define FPGA_SCANCHAIN_SIZE 2304 +`define USE_POWER_PINS 1 + // ------ Include simulation defines ----- `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`ifndef USE_POWER_PINS + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`endif // ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" +`ifndef USE_POWER_PINS + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" +`else + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v" + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v" +`endif // ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" +`ifndef USE_POWER_PINS + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v" +`else + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" +`endif `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/scff_test_post_pnr_v1.1.v"