diff --git a/MSIM/common/run_post_pnr_msim_task.py b/MSIM/common/run_post_pnr_msim_task.py
index 951d8d6..10cb27e 100644
--- a/MSIM/common/run_post_pnr_msim_task.py
+++ b/MSIM/common/run_post_pnr_msim_task.py
@@ -68,7 +68,7 @@ for testbench_file in testbench_files:
   cmd = "python3 " + msim_testrun_script_abspath \
       + " --verilog_testbench " +  testbench_file \
       + " --project_path " + msim_task_dir_abspath + "/" + testbench_name \
-      + " --testbench_name " + testbench_name
+      + " --testbench_name " + testbench_name + "_autocheck_top_tb"
   subprocess.run(cmd, shell=True, check=True) 
   num_sim_finished += 1