diff --git a/HDL/common/caravel_rtl_include_netlists.v b/HDL/common/caravel_rtl_include_netlists.v
index 02b5166..ceb5e20 100644
--- a/HDL/common/caravel_rtl_include_netlists.v
+++ b/HDL/common/caravel_rtl_include_netlists.v
@@ -8,6 +8,7 @@
 `define USE_POWER_PINS 1
 
 `include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/defines.v"
+`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/pads.v"
 
 ////////////////////////////////////
 // Skywater standard cell netlists
@@ -34,8 +35,15 @@
 `include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/user_proj_example.v"
 `include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/sram_1rw1r_32_256_8_sky130.v"
 `include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/DFFRAM.v"
+`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/DFFRAMBB.v"
 `include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/caravel.v"
 `include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/chip_io.v"
 `include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/digital_pll.v"
 `include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/mgmt_core.v"
 `include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/user_id_programming.v"
+`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/mprj_io.v"
+`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/caravel_clocking.v"
+`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/mgmt_soc.v"
+`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/housekeeping_spi.v"
+`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/clock_div.v"
+`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/storage_bridge_wb.v"