From ed92cba451a8bc2cd3898c7089db1fae630a1092 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 8 Dec 2020 15:35:38 -0700 Subject: [PATCH] [HDL] Add netlist for simulation with Caravel + FPGA --- HDL/common/caravel_gl_include_netlists.v | 41 +++++++++++++++++++ .../caravel_fpga_io_test_include_netlists.v | 3 ++ 2 files changed, 44 insertions(+) create mode 100644 HDL/common/caravel_gl_include_netlists.v create mode 100644 TESTBENCH/common/caravel_fpga_io_test_include_netlists.v diff --git a/HDL/common/caravel_gl_include_netlists.v b/HDL/common/caravel_gl_include_netlists.v new file mode 100644 index 0000000..16a6b40 --- /dev/null +++ b/HDL/common/caravel_gl_include_netlists.v @@ -0,0 +1,41 @@ +//------------------------------------------- +// A file to include all the dependency HDL codes +// required by Caravel gate-level netlists +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +`define USE_POWER_PINS 1 + +//////////////////////////////////// +// Skywater standard cell netlists +// I/O cells +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v" +// High density cells +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v" +// High voltage cells +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v" + +// Gate-level netlists +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/DFFRAM.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/caravel.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/chip_io.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/digital_pll.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/mgmt_core.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/storage.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/user_id_programming.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/user_proj_example.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/gl/user_project_wrapper.v" + +// Use RTL codes for the following module as the gate-level netlists are buggy +// in handling power pins +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/defines.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/mgmt_protect.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/mgmt_protect_hv.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/gpio_control_block.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/simple_por.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v" diff --git a/TESTBENCH/common/caravel_fpga_io_test_include_netlists.v b/TESTBENCH/common/caravel_fpga_io_test_include_netlists.v new file mode 100644 index 0000000..8a43b0f --- /dev/null +++ b/TESTBENCH/common/caravel_fpga_io_test_include_netlists.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:a13d2d93139126328833d3a1433c351eb044b0d4772ba56d214d65017a3e8c37 +size 608