diff --git a/HDL/common/wrapper_lines_generator.py b/HDL/common/wrapper_lines_generator.py
index ed31a71..80051b4 100644
--- a/HDL/common/wrapper_lines_generator.py
+++ b/HDL/common/wrapper_lines_generator.py
@@ -56,6 +56,10 @@ pin_data = json.load(json_file)
 def parse_json_pin_range(json_range) :
   pin_range_str = json_range.split(':')
   assert(2 == len(pin_range_str))
+  # If the range is in decend order, we will decrease the MSB by 1
+  if (int(pin_range_str[0]) > int(pin_range_str[1])) :
+    return range(int(pin_range_str[0]), int(pin_range_str[1]) - 1, -1)
+  # If the range is in acend order, we will increase the MSB by 1
   return range(int(pin_range_str[0]), int(pin_range_str[1]) + 1)
 
 #####################################################################
@@ -86,16 +90,16 @@ for pin_info in pin_data['pins']:
     for indices in zip(list(fpga_io_pin_range), list(caravel_io_pin_range)) : 
       # Connect all the input, output and direction port
       # FPGA input     <- Caravel input
-      curr_line = "assign " + pin_data['fpga_gpio_input_name'] + "[" + indices[0] + "] = " \
-                +  pin_data['caravel_gpio_input_name'] + "[" + indices[1] + "];";
+      curr_line = "assign " + pin_data['fpga_gpio_input_name'] + "[" + str(indices[0]) + "] = " \
+                +  pin_data['caravel_gpio_input_name'] + "[" + str(indices[1]) + "];";
       netlist_lines.append(curr_line + "\n")
       # FPGA output    -> Caravel output
-      curr_line = "assign " + pin_data['caravel_gpio_output_name'] + "[" + indices[1] + "] = " \
-                +  pin_data['fpga_gpio_output_name'] + "[" + indices[0] + "];";
+      curr_line = "assign " + pin_data['caravel_gpio_output_name'] + "[" + str(indices[1]) + "] = " \
+                +  pin_data['fpga_gpio_output_name'] + "[" + str(indices[0]) + "];";
       netlist_lines.append(curr_line + "\n")
       # FPGA direction -> Caravel direction
-      curr_line = "assign " + pin_data['caravel_gpio_direction_name'] + "[" + indices[1] + "] = " \
-                +  pin_data['fpga_gpio_direction_name'] + "[" + indices[0] + "];";
+      curr_line = "assign " + pin_data['caravel_gpio_direction_name'] + "[" + str(indices[1]) + "] = " \
+                +  pin_data['fpga_gpio_direction_name'] + "[" + str(indices[0]) + "];";
       netlist_lines.append(curr_line + "\n")
 
   # - FPGA control input ports to Caravel GPIO 
@@ -111,14 +115,14 @@ for pin_info in pin_data['pins']:
     assert(len(list(fpga_io_pin_range)) == len(list(caravel_io_pin_range)))
     for indices in zip(list(fpga_io_pin_range), list(caravel_io_pin_range)) : 
       # Connect the FPGA input port to the Caravel input
-      curr_line = "assign " + pin_data['fpga_pin_type'] + "[" + indices[0] + "] = " \
-                +  pin_data['caravel_gpio_input_name'] + "[" + indices[1] + "];";
+      curr_line = "assign " + pin_info['fpga_pin_type'] + "[" + str(indices[0]) + "] = " \
+                +  pin_data['caravel_gpio_input_name'] + "[" + str(indices[1]) + "];";
       netlist_lines.append(curr_line + "\n")
       # Tie Caravel output port to logic '0'
-      curr_line = "assign " + pin_data['caravel_gpio_output_name'] + "[" + indices[1] + "] = 1'b0;"
+      curr_line = "assign " + pin_data['caravel_gpio_output_name'] + "[" + str(indices[1]) + "] = 1'b0;"
       netlist_lines.append(curr_line + "\n")
       # Tie Caravel direction port to logic '1'
-      curr_line = "assign " + pin_data['caravel_gpio_direction_name'] + "[" + indices[1] + "] = 1'b1"
+      curr_line = "assign " + pin_data['caravel_gpio_direction_name'] + "[" + str(indices[1]) + "] = 1'b1"
       netlist_lines.append(curr_line + "\n")
 
   # - FPGA control output ports to Caravel GPIO 
@@ -135,11 +139,11 @@ for pin_info in pin_data['pins']:
     for indices in zip(list(fpga_io_pin_range), list(caravel_io_pin_range)) : 
       # Bypass the Caravel input
       # Connect Caravel output port to FPGA control output
-      curr_line = "assign " + pin_data['caravel_gpio_output_name'] + "[" + indices[1] + "] = " \
-                +  pin_data['fpga_pin_type'] + "[" + indices[0] + "];";
+      curr_line = "assign " + pin_data['caravel_gpio_output_name'] + "[" + str(indices[1]) + "] = " \
+                +  pin_info['fpga_pin_type'] + "[" + str(indices[0]) + "];";
       netlist_lines.append(curr_line + "\n")
       # Tie Caravel direction port to logic '0'
-      curr_line = "assign " + pin_data['caravel_gpio_direction_name'] + "[" + indices[1] + "] = 1'b0"
+      curr_line = "assign " + pin_data['caravel_gpio_direction_name'] + "[" + str(indices[1]) + "] = 1'b0"
       netlist_lines.append(curr_line + "\n")
 
   # - FPGA I/O ports to Caravel logic analyzer I/O only
@@ -157,14 +161,14 @@ for pin_info in pin_data['pins']:
       ##############################################################
       # SOC INPUT will be directly driven by logic analyzer 
       # since this I/O is going to interface logic analyzer input only
-      curr_line = "assign " + pin_data['fpga_gpio_input_name'] + "[" + indices[0] + "] = " \
-                + pin_data['caravel_logic_analyzer_input_name'] + "[" + indices[1] + "]" + ";"
+      curr_line = "assign " + pin_data['fpga_gpio_input_name'] + "[" + str(indices[0]) + "] = " \
+                + pin_data['caravel_logic_analyzer_input_name'] + "[" + str(indices[1]) + "]" + ";"
       netlist_lines.append(curr_line + "\n")
       ##############################################################
       # SOC OUTPUT will directly drive logic analyzer 
       # since this I/O is going to interface logic analyzer output only
-      curr_line = "assign " + pin_data['caravel_logic_analyzer_output_name'] + "[" + indices[1] + "]" \
-                +  " = " + pin_data['fpga_gpio_output_name'] + "[" + indices[0] + "];"
+      curr_line = "assign " + pin_data['caravel_logic_analyzer_output_name'] + "[" + str(indices[1]) + "]" \
+                +  " = " + pin_data['fpga_gpio_output_name'] + "[" + str(indices[0]) + "];"
       netlist_lines.append(curr_line + "\n")
 
   # - FPGA I/O ports to Caravel logic analyzer I/O and Wishbone interface
@@ -185,50 +189,50 @@ for pin_info in pin_data['pins']:
     # If this is an input pin of wishbone interface, whose postfix is '_i', we use MUX
     # otherwise, this is an output pin, we just wire the input to logic analyzer
     if (pin_info['caravel_pin_type'][1].endswith("_input")):
-      for indices in zip(list(fpga_io_pin_range), list(la_io_pin_range), list(wb_la_pin_range)) : 
+      for indices in zip(list(fpga_io_pin_range), list(la_io_pin_range), list(wb_io_pin_range)) : 
         ##############################################################
         # SOC INPUT will be directly driven by either 
         # - the Wishbone input 
         # or
         # - the logic analyzer input
         # through a multiplexer controlled by the signal 'wb_la_switch
-        curr_line = "sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_" + indices[0] + "_MUX (" \
+        curr_line = "sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_" + str(indices[0]) + "_MUX (" \
                   +  ".S(" + pin_data['mode_switch_pin_name'] + "), " \
-                  +  ".A1(" + pin_data[pin_info['caravel_pin_type'][1] + '_name'] + "[" + indices[2] + "]), " \
-                  +  ".A0(" + pin_data['caravel_logic_analyzer_input_name'] + indices[1] + "), " \
-                  +  ".X(" + pin_data['fpga_gpio_input_name'] + "[" + indices[0] + "])" \
+                  +  ".A1(" + pin_data['caravel_' + pin_info['caravel_pin_type'][1] + '_name'] + "[" + str(indices[2]) + "]), " \
+                  +  ".A0(" + pin_data['caravel_logic_analyzer_input_name'] + str(indices[1]) + "), " \
+                  +  ".X(" + pin_data['fpga_gpio_input_name'] + "[" + str(indices[0]) + "])" \
                   +  ");"
         netlist_lines.append(curr_line + "\n")
         ##############################################################
         # SOC OUTPUT will drive an output of logic analyzer 
         # since this I/O is going to interface a Wishbone input only
-        curr_line = "assign " + pin_data['caravel_logic_analyzer_output_name'] + "[" + indices[1] + "]" \
-                  +  " = " + pin_data['fpga_gpio_output_name'] + "[" + indices[0] + "];"
+        curr_line = "assign " + pin_data['caravel_logic_analyzer_output_name'] + "[" + str(indices[1]) + "]" \
+                  +  " = " + pin_data['fpga_gpio_output_name'] + "[" + str(indices[0]) + "];"
         netlist_lines.append(curr_line + "\n")
     elif (pin_info['caravel_pin_type'][1].endswith("_output")):
-      for indices in zip(list(fpga_io_pin_range), list(la_io_pin_range), list(wb_la_pin_range)) : 
+      for indices in zip(list(fpga_io_pin_range), list(la_io_pin_range), list(wb_io_pin_range)) : 
         ##############################################################
         # SOC INPUT will be directly driven by logic analyzer 
         # since this I/O is going to interface a Wishbone output only
-        curr_line = "assign " +  pin_data['fpga_gpio_input_name'] + "[" + indices[0] + "] = " \
-                  +  pin_data['caravel_logic_analyzer_input_name'] + "[" + indices[1] + "];"
+        curr_line = "assign " +  pin_data['fpga_gpio_input_name'] + "[" + str(indices[0]) + "] = " \
+                  +  pin_data['caravel_logic_analyzer_input_name'] + "[" + str(indices[1]) + "];"
         netlist_lines.append(curr_line + "\n")
         ##############################################################
         # SOC OUTPUT will drive the Wishbone output through a tri-state buffer
         # As the buffer is enabled by logic '0', we use the inverted 'wb_la_switch'
-        curr_line = "sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_" + indices[0] + "_DEMUX_WB (" \
+        curr_line = "sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_" + str(indices[0]) + "_DEMUX_WB (" \
                   + ".TE_B(" + pin_data['inverted_mode_switch_pin_name'] + "), " \
-                  + ".A(" + pin_data['fpga_gpio_output_name'] + "[" + indices[0] + "]), " \
-                  + ".Z(" + pin_data[pin_info['caravel_pin_type'][1] + '_name'] + "[" + indices[2] + "])" \
+                  + ".A(" + pin_data['fpga_gpio_output_name'] + "[" + str(indices[0]) + "]), " \
+                  + ".Z(" + pin_data['caravel_' + pin_info['caravel_pin_type'][1] + '_name'] + "[" + str(indices[2]) + "])" \
                   + ");"
         netlist_lines.append(curr_line + "\n")
         ##############################################################
         # SOC OUTPUT will also drive the Logic Analyzer output through a tri-state buffer
         # As the buffer is enabled by logic '0', we use the 'wb_la_switch'
-        curr_line = "sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_" + indices[0] + "_DEMUX_LA (" \
+        curr_line = "sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_" + str(indices[0]) + "_DEMUX_LA (" \
                   + ".TE_B(" + pin_data['mode_switch_pin_name'] + "), " \
-                  + ".A(" + pin_data['fpga_gpio_output_name'] + "[" + indices[0] + "]), " \
-                  + ".Z(" + pin_data['caravel_logic_analyzer_output_name'] + "[" + indices[1] + "])" \
+                  + ".A(" + pin_data['fpga_gpio_output_name'] + "[" + str(indices[0]) + "]), " \
+                  + ".Z(" + pin_data['caravel_logic_analyzer_output_name'] + "[" + str(indices[1]) + "])" \
                   + ");"
         netlist_lines.append(curr_line + "\n")