diff --git a/DOC/source/arch/io_resource.rst b/DOC/source/arch/io_resource.rst
index 555bde1..3666d0f 100644
--- a/DOC/source/arch/io_resource.rst
+++ b/DOC/source/arch/io_resource.rst
@@ -16,6 +16,8 @@ Among the 144 I/Os,
 
 - **115 internal I/Os** are accessible through the Caravel SOC's logic analyzer and wishbone interfaces, which are controlled by the RISC-V processor. See :ref:`io_resource_debug` and :ref:`io_resource_accelerator` for details. 
 
+.. warning:: For all the unused GPIOs, please set them to **input** mode, so that the FPGA will not output any noise signals to damage other SoC components.
+
 .. note:: The connectivity of the 115 internal I/Os can be switched through a GPIO of Caravel SoC. As a result, the FPGA can operate in different modes. 
 
 .. _fig_fpga_io_switch:
@@ -59,8 +61,8 @@ When the logic analyzer interface is enabled, the FPGA can operate in debug mode
 
 .. warning:: If the logic analyzer is not used, please configure both the management SoC and the FPGA as follows: 
 
-               - all the I/O directionality is set to input mode.
-               - all the output ports is pulled down to logic ``0``
+               - all the I/O directionality is set to **input mode**.
+               - all the output ports is pulled down to **logic ``0``**.
 
 .. _fig_fpga_io_map_logic_analyzer_mode: