From e952eb951deba9e24bc823186627046c126dc23b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 5 Nov 2020 11:29:23 -0700 Subject: [PATCH] [HDL] Add preprocessing flags for running functional verification --- HDL/common/skywater_function_verification.v | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 HDL/common/skywater_function_verification.v diff --git a/HDL/common/skywater_function_verification.v b/HDL/common/skywater_function_verification.v new file mode 100644 index 0000000..cb4312c --- /dev/null +++ b/HDL/common/skywater_function_verification.v @@ -0,0 +1,13 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Preprocessing flags to enable/disable features in FPGA Verilog modules +// Author: Xifan TANG +// Organization: University of Utah +// Date: Thu Nov 5 10:40:44 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +`define UNIT_DELAY #0.01 + +`define FUNCTIONAL 1